Cores in space: The core memory module from a 1980 Spacelab computer

Spacelab was a reusable laboratory that could be carried in the Space Shuttle's cargo bay, providing lab space for astronauts and experiments.1 Because Spacelab was a European project, it used a French-built minicomputer, the Mitra 125 MS,2 rather than the Shuttle's main computers, IBM-built AP-101 systems. For storage, the Spacelab computer contained 128 kilobytes of RAM. Rather than silicon memory, the computer used magnetic core memory, with each bit stored in a tiny ferrite ring. In this article, I take a close look at this computer's core memory system.

The core stack from the Spacelab computer. I removed the top board to show the core planes.

The illustration below shows how Spacelab fit inside the Shuttle's cargo bay. The pressurized laboratory is the cylindrical module in the front of the cargo bay, connected to the Shuttle by a tunnel. Experiments were mounted on pallets behind the laboratory. The laboratory held three identical Mitra computers.3 One computer managed Spacelab itself, while the second computer managed the experiments. The third computer provided a backup in case of failures.

Spacelab was a pressurized cylinder in the Shuttle's cargo bay, connected to the Shuttle by a tunnel. It provided a laboratory for researchers to perform experiments. This illustration of Spacelab is from NASA, C-1976-4380.

The photo below shows the core memory stack, removed from the computer. The core memory stack takes up roughly a third of the computer. The entire side panel of the computer detaches, and the core memory unit slides out. Since the computer is cooled by conduction, firmly attaching the core memory stack to the side panel kept it cool. The core memory stack consists of seven boards: a driver board, four core plane boards, a second driver board, and an interface board. Each board has two 160-pin connectors that plug into a large daughter board on each side, providing extensive connectivity between the boards. The daughter board on the right has another 160-pin connector that links the memory stack to the rest of the computer. (These connectors are the long blue connectors in the photo.)

The core memory stack in front of the Mitra computer. The circuit boards have been removed from the far side of the computer.

How core memory works

One of the hardest problems for early computers was storage. Computers of the late 1940s and early 1950s stored data through techniques such as sound waves in mercury, spots on a CRT screen, or spinning magnetic drums, but these all had limitations. What computers needed was dense, inexpensive storage that was fast, reliable, and could be accessed randomly.

During World War II, Germany developed special magnetic alloys that could "flip" from one magnetic state to another. After the war, American researchers realized that these materials could be used for storing binary data: "It was completely obvious that you could make a memory with this material," in the words of Jan Rajchman. Different aspects of core memory were patented by various inventors (including independent inventor Frederick Viehe, An Wang at Harvard, Jan Rajchman at RCA, and Jay Forrester at MIT), leading to expensive patent battles. (IBM ended up paying $400,000 to Wang—who used the money to build the computer company Wang Laboratories—and $13,000,000 to MIT.) I view Jay Forester as the most important inventor, developing the design of practical core memory, researching magnetic materials, and building the first core memory in 1953 for the groundbreaking Whirlwind computer.

Core memory is based around a tiny toroidal magnetic core, one per bit.4 A core can be magnetized clockwise or counterclockwise to store a bit. The core can be magnetized by threading a wire through the core: running a current through the wire produces a magnetic field that magnetizes the core, while running a current in the opposite direction produces the opposite magnetization.

A key problem with core memory was how to wire the cores without an absurd number of wires: if each core had a separate wire, just 16 KB of storage would require over 100,000 wires. The solution was called "coincident current addressing". The cores are arranged in a grid, with horizontal and vertical wires, as shown below. By running a current through one horizontal wire and one vertical wire, the single core at the intersection was selected. But wouldn't that magnetize all the cores along the horizontal and vertical wires? The key was that the cores were constructed from special magnetic materials with a property called hysteresis: a small current leaves the core completely unchanged, while a larger current flips the core's magnetic state. The currents through the horizontal and vertical wires were carefully selected so each wire had half the current necessary to flip the core; where the wires intersected, the two currents provided sufficient magnetic field to flip the core.

Energizing an X drive wire and a Y drive wire selects one core, highlighted in yellow. Diagram adapted from Digital Computer Components and Circuits, R. K. Richards, p355

The next step was reading the core. A sense wire was threaded through all the cores in the two-dimensional plane. To read a core, the X and Y select wires were driven to flip the desired core to the 0 state. If the core was already in the 0 state, nothing happened. But if the core was originally in the 1 state, the magnetic field changed as the core changed state. This induced a small current in the sense line, indicating that the core held a 1. Note that reading the value of a bit destroys that value. Thus, a core needs to be rewritten after reading, to restore the original data.

To access a word of memory at a time, core planes were combined into a three-dimensional stack (below). Since each plane held one bit of the word, a 16-bit word would have a stack of 16 planes. All the planes shared the signals to drive the X and Y lines, so a one-word column through the stack was accessed in parallel. Each plane had a separate sense line to read out the bit.

The core stack from the Saturn V LVDC (Launch Vehicle Digital Computer) consists of 14 core planes. This stack is at the US Space & Rocket Center. Photo from NCAR EOL. I retouched the photo to reduce distortion from the plastic case.

But how do you write different values to the different bits? The trick was to put an "inhibit" line through all the cores in a plane, running the inhibit line in the opposite direction to the X lines. Putting a current through the inhibit line would cancel out the current through the X line, preventing the core in that plane from being modified. To summarize, a read-write cycle consisted of first energizing a pair of X and Y lines to select a word and write a 0 to the column of cores in that word. The sense lines provided a readout of the bit values. Next, the X and Y lines were energized in the opposite direction to write a 1 to the cores. At the same time, the inhibit lines were energized for each plane with a 0 bit. Thus, the cores either flipped back to 1 or stayed at 0, as required. Many core memories, such as the one below, used a shared wire for sense and inhibit, so there were three wires through each core.

Closeup of an IBM 360 Model 50 core plane. The cores in this computer were called 19-32 because their inner diameter was 19 mils and their outer diameter was 32 mils (0.8 mm).

The final ingredient to make core memory practical was the diode matrix. The X and Y lines require driver circuits that can produce fast, bidirectional high-current (e.g. 600 mA) pulses. A core memory plane can have hundreds of these lines. Providing a separate driver for each wire would be very expensive, especially in the vacuum tube era. The solution was to put separate drivers at each end of the wire, with each driver supporting multiple wires. For a trivial example, suppose you have 9 vertical lines. Put three drivers (A, B, and C) on the top, each connected to three wires, and three drivers on the bottom (1, 2, and 3), each connected to three wires. By energizing a driver at the top and a driver at the bottom (e.g. B and 1), the corresponding wire will be energized. Now, N drivers on each side control N² wires, supporting N⁴ cores in total.

Illustration of how "top" and "bottom" drivers work together to select a single line (red) through the core matrix. However, current can take alternate paths, such as the pink path.

Unfortunately, it's not quite that easy. Current can take "sneak paths" through the cores, such as the path in pink above. The solution is to add diodes to ensure that current can't take the wrong path. Since a wire needs to be driven with currents in both directions (to flip cores both ways), two diodes are required on each wire, as shown below, one in each direction. Each matrix input (A, B, etc.) is replaced with two inputs, one to drive each direction. (The horizontal wires also require diodes, not shown.)

Adding diodes ensures that current only takes the desired path.

Since each wire requires two diodes, core memories used many diodes. Fortunately, diodes were small and inexpensive, so a large quantity of diodes was manageable. The photo below shows the diode stack for the computer used in the Saturn V rocket, the Launch Vehicle Digital Computer.

Closeup of the diode matrix in the Saturn V LVDC. Diodes are mounted vertically using cordwood construction between two printed circuit boards.

Originally, core memories were tediously constructed by hand. For the Whirlwind computer, it took a full 40 hours to wire a 64×64 core plane. Companies such as IBM soon developed automated techniques to manufacture core memory, and the price dropped by a factor of two every two years, similar to Moore's Law.5 Core memories became fast, inexpensive, and reliable, and were the most popular form of main-memory storage until semiconductor memory took over in the 1970s.

The Spacelab computer's core memory

The Spacelab computer's memory was manufactured in 1980, a late date for core memory, so it is advanced and high density. The photo below shows one of the four core plane boards from the computer. Each board holds 16K of 18-bit words (32 KB), so the computer has 128 KB of RAM in total. The computer is a 16-bit computer, but each word also has a parity bit and a "storage protect" bit, bringing the total to 18 bits. (The storage protect bit provided write protection on a word-by-word basis, preventing programs from being accidentally overwritten. Because core memory is nonvolatile, a program could be loaded into memory once and would be immediately available every time the computer was powered on.)

One of the core memory boards from the Spacelab computer.

The core memory board is arranged with 1024 vertical (Y) wires and 288 horizontal (X) wires, supporting 294,912 lithium ferrite cores. These very thin wires are soldered to tiny pads on the printed-circuit board. The board supports 18 bits, which is visible as 18 alternating stripes of green and copper because alternating sense lines have different colors. The board has 36 sense lines: the left and right halves of the board have independent sense lines to reduce noise, so the board has 36 sense lines for 18 bits. The sense wires pass through four holes in the board (green arrows) and are soldered on the back of the board.

The photo below shows a close-up of the cores. Each core is approximately 32 mils (0.8mm) in diameter, the same as the IBM System/360 cores shown earlier. However, the cores are stacked much closer, with only a small gap between cores. The X and Y select lines are copper-colored, while the sense lines are green. (The wires are all enameled to prevent short circuits.) The sense wires loop around at the left, forming a single circuit through each bit section. Half the Y lines form loops at the bottom; the other half form loops at the top. Thus, each Y line passes through the plane twice in a U-shaped path, which will turn out to be important.

A close-up of the cores. I think that some rows tilt left and some tilt right to ensure that the sense lines keep the same polarity when they switch direction. Photo courtesy of CuriousMarc.

The other side of each circuit board holds the sense amplifiers and the diode matrix for the core plane. The diode chips are the square black packages, each containing 16 diodes for 8 core lines.6 In the red-outlined regions, one end of each vertical U-loop is connected to a diode chip; the lines of diagonal holes are the vias that pass each signal through the board. The other end of each vertical U-loop is connected to one of the blue board connectors on the side; these vias are in the blue-outlined regions. The horizontal lines use the diode chips and vias in the green regions. One end of each line is connected to a diode chip, while the other end is connected to a board connector through traces on the other side. Note that some vertical lines connect to the diode chips at the top of the board, while others connect at the bottom. Similarly, some horizontal lines connect at the left while others connect at the right.

The back side of the core plane board holds the diode matrices and sense amplifiers.

The central region (yellow) holds 18 sense amplifier chips, the black DIP integrated circuits, each containing two amplifiers.7 The white packages are resistor packages, holding multiple resistors to bias and terminate the sense amplifier lines. The wires from the sense amplifiers are connected as twisted pairs that are soldered to the board right next to the corresponding sense amplifier chips. Using twisted pairs for the whole distance prevents the wires from picking up electrical noise, which could overwhelm the tiny signals in the sense wires. The sense wires pass from one side of the board to the other through four holes in the board (yellow arrows), and then are glued down as they traverse a significant distance on the board. (It must have been difficult to manufacture the board without breaking the tiny, fragile wires.)

Each sense wire loop forms a twisted pair that is fed to the other side through a hole in the circuit board. Above the hole, you can see a gray blob where sense wires were spliced for some reason. Also note how alternating vertical wires are soldered to the circuit board, with circular vias connected to the other side. The other vertical wires form loops. are soldered to the circuit board

Detecting signals on the sense lines is tricky because the pulses are very small, a few millivolts. Because the sense lines run next to the X drive lines, they can easily pick up noise from the high-current pulses on the X lines. To minimize this noise, the sense lines cross each other between two plane sections, forming a "bow tie", as shown below. The result is that an X line runs next to the positive sense line for half the length and the negative sense line for the other half. Thus, the induced noise cancels out.

A close-up of the sense lines. The 16 sense lines in the middle are green, while the sense lines above and below (as well as the X lines) are copper. Note that the sense lines cross, while the X lines continue horizontally. The large circles are vias through the board.

The core memory in the Spacelab computer used a different architecture from a typical core memory, improving performance by eliminating the inhibit line. This architecture was called a 2½D memory.8 If you're familiar with core memory, the lack of inhibit lines may seem puzzling: how do you write 1 to some bits and 0 to other bits? The trick is to have separate X driver circuitry for each bit.9 When writing data, the X lines are only energized for bits that receive a 1; the other lines are left unenergized, so the bits remain at 0. The disadvantage is that instead of one set of X driver circuits, you now need one set for each bit, a factor of 18 more for an 18-bit word. However, with the development of core drivers on integrated circuits, the cost of the additional driver circuitry became less significant.

The memory system used an technique called phase reversal to cut the number of vertical drivers in half. Recall that pairs of vertical wires are joined by a U-connection. By driving the wire in a particular direction, the left side or the right side of the pair can be selected. For example, the drawing below shows how the two wires select the left core, but not the right core. In the left core, both currents go through the core in the same direction, inducing a magnetic field in the toroid.10 But in the right core, the two currents cancel out, so there is no magnetic field created. But if the current in the vertical loop is reversed, the right core will be selected, rather than the left core. The point is that instead of using two drivers for the vertical wires, one driver is used, reversing the current to select the left or right core.

Connecting pairs of vertical wires into a U-shaped loop lets each driver control twice as many cores.

The diagram below shows the complex wiring for X drive wires. Each band of 16 wires corresponds to one bit in the 18-bit word, and has a separate sense wire. The top band of 16 X lines is connected to four contacts on the board connector; each contact is connected to four X lines through the curving PCB traces. The bottom band of 16 X lines is wired to diode modules on the other side of the board, connected through the round vias. (Each wire has the opposite connections—diode module or board connector—on the other end.)11 One group of four X wires is energized through the connector, while four wires are energized through the diode matrix, selecting one of the 16 X wires in the group.

The PCB wiring for the X lines.

Other boards in the memory stack

The memory stack has seven boards in total, arranged as a driver board, the four core planes, a second driver board, and an interface board. I haven't examined these boards in detail, but I'll give some preliminary information. The photo below shows one of the two driver boards. It provides the high-current pulses for the X and Y select lines. The board is crammed with specialized core memory driver chips12, along with a few logic chips to control the drivers. It has separate drivers for the two ends of the select lines, allowing the matrix selection described earlier.

One of the two memory driver boards. Click this image (or any other) for a larger version.

Since there are two driver boards and four core memory boards, at first I thought that each driver board controlled two core memory boards. The configuration turns out to be more complicated, with one more layer of matrix selections to cut the number of drivers in half. To simplify slightly, consider the X lines on a core board to have left ends and right ends, both of which must be energized to activate a line. For the left ends, the first driver board powers core boards 1 and 2, while the second driver board powers core boards 3 and 4. The right ends are shuffled: the first driver board powers core boards 1 and 3, while the second driver board powers core boards 2 and 4. Now, if the first driver board powers the left and right ends, core board 1 is the only one with both ends active. If the first driver board powers the left ends while the second board powers the right ends, core board 2 is activated. Similarly, core board 3 or 4 can be activated. The point is that since each set of drivers is connected to two core boards, two sets of drivers are required instead of four.

The final board is the interface to the rest of the computer. It has many transistor arrays in DIP packages, along with many resistors. It seems that the board uses discrete transistors to drive the bus, rather than using interface chips, which is unexpected. The board has some wire-wrapped jumpers in the lower center region, presumably for configuration.

The interface board has some unused space in the lower left.

Conclusions

Core memory had a long life, surviving even as computers migrated from vacuum tubes to transistors and then integrated circuits, but eventually semiconductor memory made it obsolete.13 Core memories lasted even longer in aerospace applications since it had two key advantages over semiconductor memory: it retained data even without power, and it was resistant to radiation. The Spacelab computer, manufactured in 1980, was near the end of core memory's reign, so it is more advanced than a typical core memory system, with higher density, extensive use of integrated circuits, and the 2½D architecture. But eventually the high density, low cost, and low power consumption of semiconductor memory won out. In 1991, the Space Shuttle flew with upgraded main computers, the IBM AP-101S that used semiconductor memory instead of magnetic core. Spacelab's Mitra computers were also replaced, using the AP-101SL, which was based on the AP-101S but modified to support the instruction set and peripherals of the original Spacelab computer.14 Although core memory is now firmly in the past, it still lives on in the expression "core dump".

I plan to investigate the Spacelab computer some more. For updates, follow me on Bluesky (@righto.com), Mastodon (@[email protected]), or RSS. Credits: Thanks to Steve Jurvetson for providing the Spacelab computer. Thanks to CuriousMarc for photography and help disassembling the computer. AI statement: Despite the presence of the em dash, no AI was used in the writing of this article (details).

Notes and references

1. It seems that 16 Shuttle flights used the Spacelab pressurized module, while 6 or 9 flights just used the unpressurized Spacelab pallets. (Why do sources never agree?) Originally, Spacelab was expected to be used for 30 flights every year (Status Of The Spacelab Program, 1974). ↩

2. The Spacelab 125 MS computer was built by a French company called CIMSA, using the Mitra architecture created by CII. I explained the complex history of these companies in my previous Spacelab computer article, so I won't go into it here.

   On the ground, the Spacelab project used Mitra 125 S computers that were functionally identical to the Mitra 125 MS (details) computers that were used in space. A core memory board from a Mitra 125 S ground computer was described on EEVblog (video, video). The computers had identical architectures, but the 125 MS was militarized and designed for "severe environmental conditions" (details). The EEVblog memory board was manufactured by Ampex and has a different design from the board that I examined.

   

   The Mitra 125 S memory board, built by Ampex. Screenshot from EEVblog #668.

    ↩

3. Spacelab was modular, so it could be be flown in different configurations. The habitable module could be flown in two different sizes, with experiment pallets mounted outside the module. Spacelab could also be flown without the habitable module, with experiments controlled from inside the Shuttle. In this case, the computers and other equipment were mounted in a smaller pressurized cylider called the "igloo". ↩

4. I'm describing "standard" core memory, but there were many esoteric designs for core memory. One approach used two cores per bit. Another approach used cores with multiple holes, such as cubical BIAX cores, transfluxors with a large hole and a small hole, or IBM's three-hole design. Many of these approaches could read a core without erasing it (non-destructive readout), but almost all cores used standard toroids. ↩

5. Later, companies discovered that it was cheaper to have core memories hand-manufactured in Asia and moved away from automated production. (See Memories that Shaped an Industry, p. 251. If you're interested in the history of core memory, this is the book to read.) ↩

6. The diode array chip is marked FSA2977 and contains 16 diodes, 8 common-cathode and 8-common anode. Pins 2 through 9 are connected to eight core wires. Pin 1 is driven high, or pin 10 is driven low, depending on the desired current direction. I couldn't find a datasheet for this part, but it appears to be similar to the Motorola MAD1103 Core-Driver Diode Array or the Silicon General SG5772F.

   ↩

   A schematic matching the diode array, from the Motorola MC1103P datasheet.

7. The sense amplifiers are National Semiconductor DS5534 chips. Each IC contains two differential amplifiers, converting the tiny sense signals into logic signals. The strobe signals indicate when the amp should read a bit; the strobes come from the IC on the left side of the board, a 54150 dual 4-input NAND gate, 50Ω line driver.

   

   Diagram of the sense amplifier, from the National Interface Integrated Circuits Databook.

    ↩

8. The 2½D memory architecture is described in detail in 2 1/2 D High Speed Memory Systems—Past, Present, and Future. Due to complicated factors and tradeoffs, the 2½D approach was attractive for systems of 16 Kword storage and above. In particular, eliminating the inhibit line boosted performance. IBM's Large Capacity Storage system used a 2½D architecture with just two wires per core to provide a megabyte of storage at a comparatively low cost, sharing the X line with the sense line. However, this approach turned out to be slow, so using three wires per core (as in the Spacelab computer) was more common. ↩

9. Note that the 2½D architecture requires separate per-bit drivers along one axis, not both. Since cores require two currents to flip, inactivating one axis is enough to prevent the corresponding cores from flipping. ↩

10. The direction of the magnetic field is given by the "right-hand rule": if you point the thumb of your right hand in the direction of the current, the magnetic field curves around the wire in the direction of your fingers.

    It may not be obvious how the currents add or cancel when the wires are in different directions. You can imagine moving the two wires until they are parallel, and then see if the currents are in the same direction or opposite. (This follows from Ampère's law, which states that the magnetic field around a curve (e.g. the core) is proportional to the net current through the corresponding surface.) ↩

11. For reference, this footnote describes the details of the core plane wiring, probably in more detail than anyone wants. For the Y lines, there are 1024 vertical lines, forming 512 U-shaped loops. Half of these are connected at the top, and half at the bottom. One end of each loop is wired directly to a connector on the side, while the other end connects to a diode matrix. The connectors provide 32 lines that can act as a source or a sink. Each of the 32 lines is connected to 16 vertical wires, for 512 vertical wires in total. Each quadrant of the board has 8 of the 32 lines, connected to a group of 8 vertical wires, a second group of 8 vertical wires, and so forth for 16 groups.

    For the diode connections, the connectors provide 16 source lines and 16 sink lines. Each diode chip has one source line and one sink line, feeding 8 vertical wires. Each source and sink line is connected to four diode chips, one in each quadrant in a mirrored pattern. Thus, the 16 source lines and 16 sink lines are connected to 64 diode chips, feeding 512 vertical loops. (Since each quadrant of the board has unique direct connections and the diode connections within a quadrant are unique, a unique core is selected. Specifically, 32 direct connections times 16 diode connections gives 512 combinations to select a vertical loop. The polarity selects which half of the loop is active, uniquely selecting one of 1024 vertical wires.)

    For the horizontal wiring, the 288 wires are grouped into 18 bands (one for each bit), with 16 wires per band. Each band has four direct signals from the connector. Each one is connected to four horizontal lines, 16 in total. (The visible PCB traces (shown earlier) connect the 16 wires to four connector pins (A,B,C,D) in the pattern AABBCCDDDDCCBBAA.)

    For the horizontal diode connections, the connector provides 4 source wires and 4 sink wires, which feed the 16 horizontal wires in a pattern 1234123412341234. By energizing the appropriate direct and diode wires on either side, one of the 16 lines is selected. One complication is that each diode chip has 8 outputs, but each source/sink goes to 4 wires. The solution is that each bit group uses half of four diode chips (4 outputs from each). Thus, the four source and sink wires are shared across two bit groups. This is not a problem for selection because the direct connections control whether the bit is active or not.

    The horizontal diodes are arranged asymmetrically. The left side has 8 diode chips at the top and 8 at the bottom, supporting 8 groups of 16 wires. The right side has 20 diode chips (4 additional in the middle), supporting 10 groups of 16 wires. Thus, all 18 bit groups are supported, with some asymmetry in the board layout.

    The left and right sides of the core plane have separate sense lines, so there are 36 sense lines in total. These go to the 18 dual sense amplifiers. Each sense amplifier has two outputs connected, a wired-OR to combine the left-hand data with the right-hand data, providing 18 bits of output to the connector.

    

    A diagram showing the topology of a core board. Click this image (or any other) for a larger version.)

    The diagram above summarizes the structure, showing one of the 18 bits. It omits the details of which connections are at the top, bottom, left, or right. ↩

12. Each driver board has 53 core driver chips of type SN55325.

    

    The SN55325 core driver chip, from the databook.

    Each chip has two 600 mA "sources" and two 600 mA "sinks" connected to two outputs. By energizing a source on one end of a line and a sink on the other end, the line can be driven in the desired direction. The driver board also has 39 driver chips of type SN55327. These chips are similar, except they can be used as either four sources or two sinks. These chips are used for the diode matrix inputs, where an input is either a source or a sink. ↩

13. I wrote about the Spacelab computer's CPU earlier. I've written about other core memory systems including the IBM 1401 core memory, IBM 360 core memory, Saturn V LVDC, and Apollo Guidance Computer. ↩

14. The Space Shuttle's replacement AP-101S computer used semiconductor memory, so it needed to deal with volatility and radiation. The new computer used battery backup to preserve memory contents when powered off, a feature that core memory had provided automatically. To avoid data corruption from radiation, the new computer had six extra storage bits for each word to implement an error-correcting code. The computer constantly scanned for bit errors and corrected them. Radiation wasn't just a theoretical risk: a single Shuttle flight could encounter over 100 bit flips due to radiation (details).

    For more information on the AP-101S computer, see my previous article, The rise and fall of IBM's 4 Pi aerospace computers. I wrote about Spacelab's original computer and the upgraded AP-101SL computer in Reverse engineering circuitry in a Spacelab computer from 1980. ↩

Energizing a vacuum-tube flip-flop module from a 1948 IBM system

In 1948, IBM introduced the 604 Electronic Calculating Punch. This machine was a programmable calculator, about the size of a double refrigerator. It was not quite a computer, but was programmed by plugging wires into a plugboard. This machine read numbers from a punch card, performed up to 60 calculations on these numbers, and then recorded the results by punching holes in the card.1 It processed 100 cards per minute—over one card per second—and IBM advertised it as the equivalent of 150 engineers. The machine rented for $550 a month, making it very popular, with over 5600 units produced.2

The IBM 604 Electronic Calculating Punch. Photo from Ed Thelen's IBM 604 page.

The IBM 604 came out just after the transistor was invented, too early to use transistors. At the time, calculators and computers were moving from slow electromechanical components to fast vacuum tubes. One of the innovations of the 604 was to combine a vacuum tube and its associated circuitry into a pluggable module. Along the left side of the photo above, you can see rows of these modules with the handles sticking out, making it easy to replace a faulty module. More modules are behind the silver metal covers. In total, the IBM 604 used about 1300 vacuum tubes.

The photo below shows a pluggable tube module, with a vacuum tube underneath the insulated handle. The nine pins at the bottom of the module plugged into a socket in the 604, with the sockets connected by backplane wiring. The vacuum tube was also socketed, so a bad tube could be quickly replaced. At the left, the resistors and capacitors are mounted on insulating wafers. Modules provided a dense way to implement circuits, packing components into three dimensions.

The TR-3 trigger module from the IBM 604 Electronic Calculating Punch.

Each pluggable tube module implemented a specific function, such as an inverter, amplifier, or power driver. The module above is a "trigger" module, type TR-3. A trigger is a circuit with two states—on and off—and can be switched from one state to the other, providing one bit of temporary storage. (In modern terminology, this is called a flip-flop.) Triggers were important building blocks in the 604, generating timing signals and storing pulses. Arithmetic in the IBM 604 was implemented with decimal counters, built from TR3 triggers.

In this article, I describe the circuitry of the TR-3 trigger module. (I recently wrote about a thyratron module in the 604; this is a different module.) After reverse-engineering the module, I powered it up. The video above shows the module in operation. By pressing buttons, I switch the trigger from one state to the other. Glowing orange neon bulbs show the state of the trigger module. The fundamental feature of the trigger is that it stays in a state until I push the other button. This might appear trivial, but the ability to store information is vitally important for computation.

How a vacuum tube works

The trigger module uses a common type of vacuum tube called a triode, which amplifies a weak signal to control a stronger signal. The diagram below shows the construction of a triode vacuum tube. The heater is a filament, similar to an incandescent light bulb, that heats the cathode to roughly 750 ºC. At this high temperature, the cathode emits electrons. If a large positive voltage (say, 150 volts) is put on the plate, the negatively charged electrons are attracted to the plate. The stream of electrons from the cathode to the plate causes a current to flow through the tube. Since air would block the electrons, the fragile glass envelope holds a vacuum, giving the vacuum tube its name. The current is controlled by the grid: if a small negative voltage is placed on the grid, it repels the negative electrons, preventing them from reaching the plate and blocking the current through the tube.3 Thus, a small signal on the grid controls the large current through the tube.

The components of a triode vacuum tube. From IBM 604 Customer Engineering manual.

The advantage of vacuum tubes was that they could switch on and off millions of times per second, phenomenally faster than electromechanical devices such as relays. The clock speed of the IBM 604 was 50 kilohertz, much below what a tube could handle, but three orders of magnitude faster than the 50 hertz pulses in an electromechanical accounting machine like the contemporaneous IBM 407.

The tube that I used in the module is called a 2033.6 This tube is a dual triode, combining two triodes into one physical glass tube. Dual triodes were very popular because they doubled the density of the circuitry. In the photo below, the two vertical black structures are the plates of the two triodes; the other structures are not visible as they are inside the plates.

The 2033 dual-triode vacuum tube.

This tube is a "miniature" vacuum tube, about 5 cm long including the seven pins at the bottom of the glass envelope.4 Since a single triode has five connections, you might wonder how a dual triode manages with seven pins instead of 10. The trick is that both triodes share the cathode and heater connections, which limits the tube to applications that don't require separate cathodes.

One disadvantage of vacuum tubes is that the heater uses considerable power. This tube's heater requires 6.3 volts at 300 milliamps—almost 2 watts per tube. Using 6.3 volts may seem a bit random, but many vacuum tubes used this voltage for historical reasons: this was the typical voltage provided by a 6-volt automobile battery.5 In the photo below, you can see the orange glow from the two heaters, mostly hidden by the plates but visible at the top and bottom.

The tube powered up, showing the glowing filaments.

Inverters and the trigger circuit

The trigger circuit is based on two inverters, so I'll start by explaining the tube inverter circuit.7 The idea of an inverter is to amplify and invert the input signal: a "low" input results in a "high" output and vice versa. First, consider a low input: if a negative voltage is applied to the grid, the flow of electrons is blocked, turning off the tube. In this case, the resistor pulls the output high with 150 volts. However, if a positive voltage is applied to the grid, the tube turns on and conducts current. This current pulls the output down, due to the voltage drop across the resistor, producing a low output of 50 volts. Thus, a low input causes a high (150 V) output, while a high input causes a low (50 V) output, providing the desired inverter action. Note that the input signal has a swing of over 50 volts, very large compared to a transistor circuit. Moreover, the output voltages are much higher than the input voltages, which is somewhat inconvenient when connecting circuits.

An inverter circuit. Adapted from IBM 604 CE Manual.

A trigger is constructed from two inverters connected in a loop. The output of the first inverter is fed into the second inverter, and the output of the second inverter is looped back to the first inverter. If the first inverter has a high output, the second inverter has a low output, which is fed back to the first, maintaining the high output from the first inverter. The situation is similar but opposite if the first inverter has a low output. Thus, this circuit has two stable states, with one inverter on and the other off.8 Once the circuit is placed into a state, it will remain in that state until forced into the other state.

Two inverters in a loop can store a 0 or a 1.

I reverse-engineered the TR-3 module, creating the schematic below.9 It's a bit tricky to see the loop of inverters because the two inverters share one tube and are wired in a cross-coupled arrangement. In brief, one inverter uses the left half of the tube and the other uses the right half. The plate output from one side is wired to the grid input on the other side, through 200K and 1K resistors. The two module outputs (pins 7 and 8) are taken from the plates, but output 8 has a resistor between it and the plate. As a result, the two outputs provide different voltage levels, making the module more flexible to use.10 The two inputs force the trigger into one state or the other. The inputs are connected through 40 pF capacitors, providing AC coupling so the inputs can use different voltage levels from the outputs.

Reverse-engineered schematic of the TR-3 trigger module. Note that the pin numbers for the module are different from the pin numbers for the tube.

One tricky part is the connection between one inverter's output and the other inverter's input. The problem is that the output voltage is 50 to 150 volts, but the input grid voltage must be close to zero (a bit positive or a bit negative). The solution is to use a large negative voltage (-100 volts) and a resistor divider as a level shifter. With a large positive voltage from the plate and a large negative bias voltage, the resulting grid voltage ends up being moderately positive or moderately negative. As a result, the circuit requires both a high positive voltage (for the plate) and a high negative voltage (for the bias), complicating the power supply requirements.

The inputs are fed into the grid through capacitors, allowing a pulse to pass through the capacitor to the grid. You might expect that a positive pulse would turn on the triode, but the module was used in the opposite way, with a negative pulse to turn off the triode. (This direction is more sensitive, because a tube has more gain when it is on.) Thus, a negative pulse on the left input will turn off the left side. The plate output of the left side goes high, pulling the gate of the right side high, turning the right side on. The plate output from the right side goes low, pulling the gate of the left side low, keeping the left tube off. Similarly, a negative pulse on the right input turns off the right side, causing the left side to turn on. Multiple pulses have no effect; that side remains off. Positive pulses also have no effect; the circuit is designed so a positive pulse is not sufficient to turn a triode on.11

I found the trigger circuit to be somewhat temperamental: the trigger needs to be stable enough to stay in one state or the other, while also unstable enough that an input pulse will reliably flip it to the other state. The circuit depends on carefully balancing the grid voltages and the input voltages. I experimented with different supply voltages and found that in some cases the trigger would oscillate, while in other cases, the trigger would get stuck in one state. Interestingly, the later IBM 650 computer abandoned this type of trigger circuit, instead using diode logic (AND and OR gates) to set and reset a loop of two inverters. With this type of trigger, the state is determined by reliable Boolean logic, rather than analog interactions of changing voltages.

Conclusion

The development of the trigger is an under-appreciated step in the history of digital computers. Because the trigger holds information—state—it can be used to create a state machine. This allows a computer to perform operations step by step, rather than a jumble of actions all happening at the same time.

The trigger circuit dates back to 1918, when two British physicists, William Eccles and Frank Jordan, invented a circuit that used two cross-coupled triodes to create a circuit with two stable states. They viewed this circuit as a type of relay, triggered by a small signal and retaining its state until it was reset. They patented the circuit (Improvements in ionic relays) and wrote about it: A Trigger Relay Utilising Three-Electrode Thermionic Vacuum Tubes. (The Eccles-Jordan trigger circuit below is conceptually similar to the TR-3 trigger module, using cross-coupled triodes. One difference is that the input is coupled with a transformer.)

A diagram of the Eccles-Jordan trigger relay, from their 1919 paper.

The Eccles-Jordan trigger eventually led to digital counters. In 1939, the journal Electronics published an article Trigger Circuits, describing how trigger circuits could be combined to construct high-speed counters. One problem was that triggers can be easily combined to count in binary, but in the 1940s, calculating and accounting machines generally used decimal numbers, not binary. In the groundbreaking ENIAC computer (1945), bulky counters were constructed by putting ten triggers in a ring to count each decimal digit. IBM engineers invented a more efficient decimal counter that used four triggers instead of ten, coming up with binary-coded decimal (BCD) and obtaining a 1946 patent: Electronic Counting Circuit. IBM used this counting circuit in the 603 Electronic Multiplier (1946), followed by the 604 Electronic Calculating Punch (1948).

Modern computers use triggers—albeit under the modern name "flip-flops"—by the millions, but now they are microscopic transistor circuits instead of vacuum-tube modules.

For updates, follow me on Bluesky (@righto.com), Mastodon (@[email protected]), or RSS. Thanks to Robert Garner for providing the module and to CuriousMarc for hardware support. AI statement: Despite the presence of the em dash, no AI was used in the writing of this article (details).

A 1951 advertisement for the IBM 604, describing how the system was like having 150 extra engineers. Slide rules were the common calculating tool at the time. Notice that diversity amongst engineers was limited to hairstyle. From Fortune, December 1951 via Wikimedia, scanned by Michael Holley.

Notes and references

1. The punch cards were read and punched by a separate unit, the IBM 521 Card Reader/Punch, which was connected to the IBM 604 through a thick cable. The 521 had a card magazine on the upper left to hold cards to be read. After cards were processed, they were collected in the hopper in the middle of the 521. Note the plugboard control panels in both the 604 and the 521.

   

   The IBM 521 Card Reader/Punch to the right of the IBM 604 Electronic Calculating Punch. Photo from Customer Engineering Manual of Instruction.

   The punch cards were standard IBM 80-column cards, introduced back in 1928. The position of a hole in a column indicated the digit value for that column. For a particular task, the 80 columns would be divided into fields to hold various numbers. The 604 only supported numbers, not other alphanumeric symbols. A negative number was indicated by punching an additional hole over the units digit, using the second row from the top. (This was called an "X-punch", unrelated to the letter X.)

   

   Punch card code, from IBM 29 Card Punch Reference Manual. This code is somewhat later, with a variety of special characters.

    ↩

2. An interesting video showing the manufacturing and operation of the IBM 604 is here. For information on the IBM 604, see the Operating Manual. The Customer Engineering Manual of Instruction explains the 604 in detail, showing a TR-3 tube module on page 20. See IBM's Early Computers for information on the development of the 604. ↩

3. You can think of a triode as analogous to an NPN transistor, with the grid as the base, the plate as the collector, and the cathode as the emitter. ↩

4. The IBM 604 also used dual-triode vacuum tubes with nine pins, rather than seven, such as the type 5965. (Seven and nine pins were standard sizes for tubes.) The nine-pin tubes had separate connections for each cathode; this allowed the tubes to be used in circuits such as "cathode followers". The two filaments were in series, sharing a common "middle" pin, which is why the tube used nine pins instead of 10. ↩

5. For a discussion of filament voltages, see Valves, 1939. This article discusses how car radios motivated the use of 6.3 volt filaments in the United States, where 6-volt car batteries were common. ↩

6. The 2033 tube is very similar to the popular 6J6 tube, but optimized for computer circuits. The IBM 1684 tube is also very similar. The tube module that I examined was missing its tube, so I can't guarantee that the 2033 is the correct tube. ↩

7. The standardized tube modules weren't as standardized as one might expect. For instance, the 604 used 27 different types of inverter modules in total. For a detailed discussion of the tube inverter, see IBM 604 CE Manual, pages 26-41. ↩

8. A trigger circuit is symmetrical, so how do you define whether a trigger circuit is on or off? IBM's convention was that if the left triode was conducting, the trigger was on, while if the right triode was conducting, the trigger was off. See IBM 604 CE Manual, page 54. ↩

9. The 604 manual includes a schematic of the TR-3 module (and other modules). Inconveniently, I didn't find this schematic until I had reverse-engineered the module; I made minor adjustments to my schematic based on this. This schematic is a bit tricky to interpret. All the resistances are in thousands of ohms (e.g. 1 is 1 KΩ), and capacitances are in "micromicrofarads" (i.e. pF). The circled numbers indicate pins of the module, while numbers in square boxes indicate voltages according to an obscure standard: 2 is +150V, and 5 is -100 V. "2-110" and "300638" are IBM part numbers. "6J" indicates that the tube is in the 6J family, where 6 indicates the heater voltage and J indicates a triode. The 604 documentation used cryptic boxes as symbols for the modules, with the arrows indicating the inputs and outputs; note that output 7 is at a lower position than output 8, indicating a lower voltage level.

   

   Schematic from the CE Manual of Instruction, page 260.

    ↩

10. The two outputs from the trigger module are at different voltage levels. The idea is that a circuit could use either output, depending on which voltage level was more convenient. The asymmetrical outputs caused me great trouble, however, since I wanted to attach neon bulb indicators to show the state of both outputs. I had to carefully adjust the voltages so that the bulbs had enough voltage in the "on" state to turn on, but also a sufficiently low voltage in the "off" state to turn off. (When a neon bulb turns on, the neon gas ionizes, so it requires a significantly lower voltage to turn the bulb off.)

    The IBM 604 used neon bulbs to show the state of various circuits, both in the front panel and internally. However, unlike me, IBM used a single bulb for each trigger, either on or off, so the inconsistent voltage levels didn't cause problems. ↩

11. The 604 used 12 different types of trigger modules, from TR-1 through TR-42. The different trigger circuits were similar, but had different component values to tune the characteristics, as well as different resistors for the output levels. A few types used resistive inputs instead of capacitively coupled inputs.

    The trigger modules were used in a variety of different ways. Briefly removing the negative bias from one side would turn that side on; this was used for reset circuits. Second, a plate could be pulled low, turning off the tube on the other side. Third, the input could be connected directly to the input, rather than going through a capacitor, with a negative voltage turning the triode off and a positive voltage turning the triode on. Other triggers used a capacitor between the plate and grid on each side to filter out noise and contact bounce. Some triggers used capacitor inputs (as in the module I described), but fed the same negative input pulse to both sides. The pulse is ignored by the triode that is on, but flips the triode that is off. The result is that the trigger switches state on each pulse—analogous to a toggle flip-flop—and divides the input pulses by two. ↩

Examining circuit boards from the Space Shuttle's I/O Processor

The Space Shuttle's five1 general-purpose computers played a critical role in each flight: controlling the engines, monitoring thousands of sensors, displaying data to the astronauts, and navigating the Shuttle. Each computer consisted of two 60-pound aluminum-alloy boxes: the box on the right is the CPU, a 32-bit processor that executed 420,000 instructions per second. These computers were designed before microprocessors became popular, so the processor was built from multiple boards crammed with simple chips and they used magnetic core memory rather than DRAM chips.

The Space Shuttle IOP and CPU (AP-101B). Photo courtesy of RR Auction.

The box on the left is the I/O Processor (IOP): the link between the CPU and the rest of the Shuttle. It implemented the input/output capabilities for the computer, primarily 24 high-speed networks that connected the computer to the Shuttle's systems and sensors. But the IOP wasn't just a peripheral; it was a separate programmable computer, more complicated than the main CPU. The IOP had an unusual architecture: it was one of the first multi-threaded computers, implementing 25 virtual processors (with two completely different instruction sets) that ran on one physical processor.

I obtained two circuit cards from the I/O Processor,2 each a 9"×3" rectangle packed with tiny chips and other components. In IBM lingo, each card is called a "page" (remember this term). The top page is a network interface, providing four network connections, each handling 1 million bits per second. (The IOP contained six of these cards for its 24 network connections.) The bottom page held the microcode for the IOP's processors, the low-level code that defined each instruction. The rows of white-and-gold chips stored the microcode's bits in tiny metal fuses, programmed by blowing a fuse for each 1 bit. In this article, I'll explain how the I/O Processor worked, and the roles of these two pages.

Two pages from the Space Shuttle I/O Processor: the "MIA" interface page and the PROM page.

The MIA interface page

The Space Shuttle had 28 data bus networks that linked the computers to the rest of the Shuttle, with each computer attached to 24 of the networks.3 The large number of networks provided both high performance and reliability, with at least two networks between a computer and any Shuttle system. Eight networks were assigned to flight-critical systems, with each CRT display and engine controller connected to four networks for redundancy.

The page below is one of the six network interface pages in the I/O Processor. Space Shuttle engineers loved acronyms, so this page has the cryptic name MIA for "Multiplexer Interface Adapter". (Many of the networks were connected to boxes called Multiplexer/Demultiplexers, which provided the link between the network and the diverse analog and digital components of the Space Shuttle.5) The MIA interface page is tightly packed with integrated circuits and other components. The page holds two printed-circuit boards, one on each side of the page. The boards on both sides are almost identical,4 as you can see by comparing the photo above and the photo below. (Main difference: the connector switches sides.)

The network interface page, called the MIA (Multiplex Interface Adapter). The page has extensive rework; thin brown "bodge" wires snake around the page to repair errors or implement updates.

Each board implements two network interfaces, so the page supports four networks. Each network transmits data across a pair of wires, twisted together and shielded, rather than a coaxial cable. Although the network transmits digital data, the signals transmitted across the network are physical voltages that will weaken with distance and will have distortion and noise. Thus, the interface page must convert these analog signals back to 0's and 1's.

The right half of the board holds the analog circuitry. It is dominated by a large golden module labeled "IBM", with 46 pins. This is a hybrid module, consisting of tiny components such as transistor dies, resistors, capacitors, and potentially IC dies, connected by bond wires thinner than a hair. It's not quite an integrated circuit, but a collection of individual components mounted on a ceramic wafer. Hybrid modules were popular for aerospace applications, since a board of analog components could be shrunk down to a single (expensive) module. This module contains the analog circuitry for two I/O ports: the drivers to transmit network signals along with the amplifiers and comparators to receive signals.

Various discrete components are mounted next to the hybrid module: resistors, glass capacitors6, inductors, and small square transformers. The transformers provide the coupling between the interface board and the network. As with Ethernet, transformers provide isolation between the computer and the network, filter electromagnetic interference, and match impedances, all important for reliability.7

The Manchester Mark 1; Prof. Williams is second from the left. Photo from the University of Manchester.

A key part of the Shuttle's networking dates back to the 1940s. In 1946, Frederic Williams became head of the Electrical Engineering department at the University of Manchester. By 1949, his team had created the groundbreaking Manchester Mark 1 computer. Along the way, they invented the stored-program computer, the Williams tube—the best form of computer memory before magnetic core—and the Manchester Carry Chain, still used for addition in modern processors.

But the relevant invention is the patented Manchester encoding, a way of encoding a sequence of 0's and 1's for storage or transmission. In the Manchester encoding, each 0 bit is replaced by a "low-high" sequence and each 1 bit is replaced by a "high-low" sequence, as shown below. This idea may seem trivial, but it is used in everything from floppy disks and remote controls to Ethernet and RFID tags, earning it recognition as an IEEE Milestone.

A diagram illustrating Manchester encoding. From Prototype IOP Functional Description, p82.

The obvious approach—sending binary data unencoded—has two problems. First, in a long string of 0's or 1's, it is hard to tell how many bits were sent: "Was that six bits or only five?" Second, such a sequence is unbalanced, so it has a "DC component". This DC component causes problems if the signal is stored on a magnetic medium or transmitted through a transformer. The Manchester encoding solves both these problems. Since every encoded bit has a transition in the middle, it is straightforward to separate the bits. Moreover, the encoding ensures that 0's and 1's occur in equal numbers, so there is no DC component.

Because of these advantages, the Manchester encoding was selected for the data bus networks in the Space Shuttle.8 One of the key functions9 of the IOP's network interfaces is to convert between serial bits and the Manchester encoding. The digital circuitry for the interface is fairly complicated, but most of the logic is in the four large golden integrated circuits. These are custom Motorola integrated circuits: a transmit chip and a receive chip for each network port. On the transmit side, the chip converts binary data into the Manchester-encoded signals for the network. The circuitry also inserts a sync signal at the beginning of each word and adds parity. The receive chip reverses this process: detecting sync, decoding the Manchester signals, verifying the parity, and reporting any errors.

The smaller black chips are simple TTL chips, mostly shift registers. (Transistor-Transistor Logic was very popular in the 1970s, providing fast, reliable circuits.) There are twelve 4-bit shift register chips and sixteen 8-bit shift registers.10 The Shuttle's networks sent 24-bit words across the network: combining six 4-bit shift register chips produces a 24-bit shift register, which converted these 24-bit words to serial data and vice versa. The remaining chips are simple logic gates, flip-flops, buffers, and four-bit counters.

The physical structure of a page

Around 1967, IBM introduced a line of computers for avionics, called System/4 Pi.11 These systems were constructed from pages:12 two circuit boards sandwiching a metal layer that provided conduction cooling. Flat-pack integrated circuits, smaller than a fingernail, were mounted in rows13 on each circuit board, about 78 ICs on a board. The printed-circuit boards were advanced for the time, with six layers of wiring. Two jack screws at the top tightly secured the page into the system. Two 98-pin connectors connected the page to the backplane. The photo below shows a typical 4 Pi page (top), with its rows of chips.

A comparison of a standard IBM 4 Pi page with the IOP page. 4 Pi page courtesy of Eric Schlaepfer. The 4 Pi page was in a bag labeled "FSD AWACS tester?" suggesting that it was a tester from IBM's Federal Systems Division for the E-3C Airborne Warning and Control System aircraft, which used an IBM 4 Pi computer.

An I/O processor page (above, bottom) is almost identical to a standard 4 Pi page except that it is one inch wider (9" instead of 8"), and has a 120-pin connector or two instead of 98-pin connectors.14 One inch may not seem like much, but a 9-inch page fits 100 ICs rather than 78, a significant increase. I'm surprised that IBM changed from the standard size, but I suspect that the designers couldn't fit the IOP into the available space with standard pages, forcing the change. Likewise, the multiple I/O ports may have required more connections than the smaller connectors could support.

A page has circuit boards on either side, separated by a metal plate. To allow signals to flow between the boards, a special connector is attached to the top of the page to link the two boards. This connector not only provides feed-through connections between the boards, but also provides test points, so signals can be probed while the boards are mounted in the case. The photo below shows a close-up of the feed-through connector. It has three rows of test points. The first row (red) is connected to the top board. The middle row (orange) is connected to both boards and provides the feed-throughs. The bottom row (blue) is connected to the bottom board. The upper arrows show where the connector is soldered to the board.

The test point connector on the MIA page.

The diagram below shows the construction of the I/O Processor, with rows of pages plugged into the backplane.15 Note the 128-pin MIA I/O connector on the front of the IOP; this connects the 24 data buses (along with other signals) to other parts of the Shuttle. The arrows show how cooling air flowed through the sides of the IOP. The air did not flow over the pages. Instead, heat was transmitted by conduction through the metal plate inside each page, flowing to heat exchangers in the sides of the case. The CPU and the IOP both contained magnetic core memory (labeled "Storage Page" below); even though the memory is split between the boxes, it is treated as a unified shared memory, so programs for the CPU and the IOP can reside in memory in either physical box.

Exploded view of the IOP. From Prototype IOP Functional Description.

The IOP's architecture and the PROM page

The high-performance design of the I/O Processor was developed by Peter Kogge, an expert in parallel processing architectures. At the time, he was working at IBM's Federal Systems Division, where the Space Shuttle computer was developed.24 Kogge, now a professor at the University of Notre Dame, is also known for the Kogge-Stone adder, a fast circuit used in processors such as the Pentium. The I/O Processor has a very unusual architecture: although it had one physical processor, it ran 25 virtual processors with two completely different instruction sets. The virtual processors took turns, running for just one clock cycle and then letting the next processor run. The motivation behind this was to ensure that each network port got a predictable and guaranteed portion of the processor, so even if one network port was overloaded, it wouldn't affect the others. This approach, called a barrel processor16, was first used in the CDC 6600 supercomputer, the world's fastest computer from 1964 to 1969.

The I/O Processor has two types of (virtual) processors, which of course have cryptic acronyms: BCE and MSC. Each of the 24 network ports has a BCE, a Bus Control Element, which runs a small program to move data words between the network port and memory. An MSC (Master Sequence Controller) is the executive, running programs to manage the BCEs. The BCE and MSC processors run code that is stored in the computer's core memory. The instruction sets of the MSC and the BCE are completely different from each other and from the instruction set of the main CPU (which is derived from IBM's System/360 mainframes). The (executive) MSC is a 32-bit processor with the standard instructions of a normal processor—addition, logic, branches, and so forth—as well as specialized operations to configure and start BCEs.17 The instruction set of a low-level BCE is much smaller and much stranger, lacking all the basic instructions such as arithmetic and conditional branches. the instructions you'd expect from a processor. Instead, a BCE has I/O instructions such as Transmit Data, Receive Data, Load Timeout Register, Store Status, and Wait. In typical use, the CPU directs the MSC to run a program, the MSC configures the BCEs to execute a program, and the BCEs send and receive data as specified. When the BSE's operation is done, the MSC interrupts the CPU, which processes the data. Thus, the CPU can focus on the high-level algorithms without wasting cycles on network operations.

How do the MSC and BCE processors all run on one physical processor, when they have completely different instruction sets? The trick is microcode: each MSC and BCE instruction was implemented in microcode, through a sequence of 72-bit micro-instructions.18 A simple instruction might take five micro-instructions, while a complex instruction might require 60 micro-instructions. Each micro-instruction directed the action of the IOP's physical processor for one step of the MSC or BCE instruction. After each micro-instruction, the physical processor switched to the micro-instruction for the next virtual processor. The architecture of the physical processor was completely different from the MSC or the BCE: three 16-bit data paths and two ALUs (Arithmetic/Logic Units) that can operate in parallel. The physical processor had a separate register set, including a micro-instruction address register, for each virtual processor, to keep track of the state of each virtual processor.

The PROM page holds the majority of the microcode for the I/O Processor. Although three chips are mounted sideways to avoid wasting space, there is even more wasted space at the left.

The IOP's micro-instructions were stored in the PROM page above. In the photo above, the white chips with gold lids are fusible-link PROM (Programmable Read-Only Memory) chips.19 These unusual chips contain a tiny fuse for each bit. If the fuse is intact, the corresponding bit is a 0, while a burnt-out fuse represents a 1 bit. The chip is programmed by applying 17-volt pulses to destroy fuses one by one, literally burning the PROM. (I discussed fusible PROM chips earlier.)

Each PROM chip holds 512 words of 4 bits, so in total, this page held 1024 72-bit micro-instructions; the remaining 512 micro-instructions were in another page.20 The chips are hand-labeled with numbers, since each chip has unique programming and must be installed in the correct location. With 36 chips, you'd expect the chips to be numbered from 1 to 36. Curiously, although many of the chips are sequentially numbered, others have numbers ranging from 55 to 74 in no obvious pattern.21

Physically, the PROM page is unusual in several ways. Instead of flat-pack integrated circuits, it uses DIP (Dual-Inline Package) ICs, larger integrated circuits with two rows of vertical pins that go through the circuit board. Since this page only has one circuit board, it doesn't have the test-point feed-throughs at the top. It still has the central metal plate, but the integrated circuits sit on top of the metal plate, while the circuit board is underneath—the plate has gaps for the pins. Between the rows of chips, the central plate is the full thickness of the board.

A close-up of the PROM page, showing how the chips are mounted. The black chips are much thicker than the white chips.

Presumably, the fusible-link PROM chips were only available in DIP packages, rather than flat-packs. These DIP packages take up much more space than the regular flat-pack integrated circuits; this page has about a quarter the density of a regular page.22

Conclusions

The Space Shuttle's CPU and IOP were advanced when they were designed, but they rapidly became obsolete. IBM redesigned the computer, combining both the CPU and IOP into a single box called the AP-101S, which first flew in 1991 (details). The improved computer was much faster and had more memory. Moreover, combining two boxes into one saved about 300 pounds in total. The photo below shows three of the updated AP-101S computers mounted in the Shuttle's avionics bays. (The wall hides the fourth computer, and the fifth is behind the camera.) These same positions are where the I/O Processors were mounted previously, with the CPUs installed in the empty spaces to the left.

Avionics bays 1 and 2 are located in the crew cabin middeck, below the flight deck, and looking forward into the nose. The red arrows indicate the AP-101S computers. The remaining computer is in avionics bay 3A, on the aft right side of the middeck. This photo is from 2011, showing Discovery being prepared for display at the Smithsonian. Original photo courtesy of collectSpace; I've adjusted the lighting.

Despite the critical role of the I/O Processor in the Space Shuttle, it doesn't get the attention given to the CPU. For instance, although NASA documents describe the architecture of the IOP in detail, I couldn't find any photos of its pages.23 I hope that this article has convinced you that the architecture and the physical construction of the IOP make it an interesting system.

For updates, follow me on Bluesky (@righto.com), Mastodon (@[email protected]), or RSS. Thanks to Richard for supplying the boards. Thanks to Mike Stewart for documents on the IOP. Thanks to Robert Pearlman of collectSPACE, and RR Auction for photos.

AI statement: I didn't use AI to write this article; the em-dashes are natural (details).

Notes and references

1. On some flights, a sixth computer was carried in a locker as a spare, providing an additional degree of reliability. If one of the five computers failed, the astronauts could connect the cables to the spare computer and it could take over for the failed one. The spare was put into use on flight STS-30 (1989) after computer #4 encountered a "data parity external storage error", indicating a hardware problem. ↩

2. I suspected that these pages were from the I/O Processor, but it was difficult to prove this. Fortunately, Mike Stewart found a document, the Prototype Input/Output Processor Function Description, that lists the pages in each IOP slot. The MIA page has a part number on it: 6246523-3, and the PROM page has 6104848-3; these match "MIA" 6246523-1 and "Micro Store (ROM)" 6104848-1 in the document. ↩

3. The diagram below shows how the 28 data bus networks connect the five computers at the top and various parts of the Shuttle. The networks are categorized as ground interface, mission critical, flight instrumentation, display system, mass memory, intercomputer, and flight critical.

   

   Data bus architecture. Click for a larger version. Adapted from Space Shuttle Avionics Systems.

   Why was each computer connected to 24 networks and not all 28? Each Space Shuttle computer was connected to almost all the networks, so they could run in lockstep for reliability. The exception was that each computer sent its own monitoring data to the ground station. Since this data was of no importance to the other computers, it was sent over a private network called Flight Instrumentation to the PCM (Pulse Code Modulation) box, which encoded the data for transmission to the ground. There were 23 shared networks and 5 private networks (one for each computer), so there were 28 networks in total, with 24 networks connected to a particular computer. ↩

4. Both sides of the interface page are almost identical. However, the connector is on the left or the right side, depending on which side of the page you examine. This forced the decoupling capacitors at the very bottom to move to accommodate the connector. I also found a single integrated circuit that was different between the two sides, for some reason. ↩

5. While many of the data bus networks are connected to a Multiplexer/Demultiplexer (MDM), this is not always the case. Networks were also connected directly to systems such as an Engine Interface Unit or a Display Electronics Unit. Moreover, the MDM was not necessarily the final step between the network and the Shuttle's sensors. The MDM held cards to support over a dozen types of input and output signals: digital, analog, on/off (discrete), and serial. However, the thousands of signals in the Shuttle were much more diverse; sensors can provide AC signals, pulses, thermocouple values, resistances, and so forth. Other boxes converted the raw sensor signals into forms that the MDM could handle; these boxes were called Dedicated Signal Conditioners (DSC). A DSC had 15 or 30 slots to hold cards to perform the necessary signal conversion. Thus, the MDMs and DSCs combined a fixed architecture with the ability to be customized for each role. ↩

6. The glass capacitor is an interesting component, with an extremely thin layer of glass as the dielectric. Glass capacitors became popular in the 1960s for aerospace applications because of their stability and reliability (more). These capacitors were manufactured by Corning Glass Works, as indicated by the "CGW" label on the package.

   

   Two glass capacitors on the MIA page.

   The capacitor is labeled with a military code. "J" indicates the Joint Army/Navy specification. "CY" indicates a glass capacitor, "4" apparently indicates axial leads, "G" indicates the temperature/voltage, "510" is the value (51×10⁰ = 51 pF), and "G" indicates ±2% tolerance. (I don't know why one capacitor has "0F" and the other has "4G".) ↩

7. The Space Shuttle had a second layer of transformers between the computer and the network, ensuring a faulty device didn't bring down the network. Each device (such as the IOP) was connected to the network through a tiny device called the Data Bus Coupler. This one-inch cube contains a transformer and a few resistors to match impedance. The coupler acts as a network tap, providing a short stub from the network to a device. The coupler also provides line termination if the device is removed, ensuring signal integrity. ↩

8. The Space Shuttle's network is very similar to the U.S. military's serial network standard MIL-STD-1553. The 1553B standard is widely used in numerous military aircraft, missiles, tanks, navy systems, the Airbus A350 commercial plane, and the James Webb Space Telescope. However, since the Space Shuttle's network and the 1553 standard were both under development in the early 1970s, the two networks are not the same. The main differences are that the Shuttle uses 24-bit words instead of 16, and has 5.5µs gap between words (details). ↩

9. The functions of the MIA are described as:

   • Transmit and receive data
   • DC isolation
   • Parallel/serial conversion
   • Serial/parallel conversion
   • Sync generation and detection
   • Manchester encode and decode
   • Parity generation and detection
   • Bit count detection
   • Provide status to BCE.

   The functional block diagram below shows the circuitry for one port of the network interface. This circuitry is replicated twice on each board; with a board on each side of the page, the page supports four networks. The dashed Transmitting and Receiving boxes correspond, I think, to the large Motorola chips, except that the "TX" and "RX" amplifiers are in the IBM hybrid module and the transformers are discrete components.

   

   Functional block diagram of the MIA. From Prototype IOP Functional Description, p82. Click for a larger image.

    ↩

10. The 4-bit shift register chips are 54LS395 chips. These chips have "tri-state" outputs, allowing them to be connected to a bus. These chips probably provide the interface between the board and the rest of the IOP; the twelve chips on a board would support a 24-bit register for each port, as expected. The 8-bit shift register chips are 54LS1964 shift registers.

    I can't figure out why there are so many 8-bit shift register chips; perhaps they act as buffers. My speculation... The Prototype IOP Functional Description states that the IOP has six 28-bit 4-word registers between the 24-bit MIA shift registers and the rest of the IOP. Could the 8-bit shift register chips form these registers, even though shifting is not necessary? The document doesn't make it clear if these registers are on the MIA page or a different page. The shift-register chips provide 256 bits of storage per page, while the register file needs 112 bits, so there are way more bits than required. Moreover, the document says that the registers are structured as 7-4&4 register files for each set of four MIAs, which sounds more like 54LS170 register file chips (for instance) than shift-register chips. Possibly, the design was modified from the Prototype Functional Description, and the 8-bit shift registers provide additional buffering. ↩

11. The 4 Pi name is a geometry joke based on IBM's wildly popular series of mainframes, the System/360. System/360 revolutionized the computer industry with the concept of one family of computers for all applications: business and scientific. The name symbolized that System/360 covered the full 360º of applications. The 4 Pi name extended the idea of a circle to the 3-dimensional world: 4π is the number of steradians making up a full sphere. As IBM put it, "System/4 Pi also fills a sphere—the full spectrum of military computer needs—for airborne, space, or shipboard use." ↩

12. The earliest 4 Pi systems (the TC line) used a different style of page, but the following computers used the standard 4 Pi pages, including the Space Shuttle's AP-101B computer. However, IBM moved to much larger pages, starting with the next computer, the AP-101C in the B-1 bomber. The Space Shuttle's upgraded computer, the AP-101S, used these larger pages. For details, see my article on 4 Pi computer history. ↩

13. The photo below shows how the flat-pack integrated circuits are mounted on the circuit board. 16 pads are allocated to each integrated circuit; 14-pin integrated circuits "waste" two pads, while larger integrated circuits break the regular pattern. Each pad is connected to a via, a plated hole through the circuit board. These vias provide connections to wiring traces on a different layer of the circuit board; some of these traces are visible in the photo. Vias also hold the leads of through-hole components. The circuit cards in IBM System/360 mainframes used a very similar style of printed-circuit board, with a regular grid of vias. This style of board is very different from the circuit boards used in most other systems, which only had holes where necessary and routed traces less regularly. IBM's style presumably made hole drilling more efficient and was easier for automatic routing, but required thin, precise traces and multi-layer circuit boards, which were not common at the time.

    IBM's technology was highly advanced compared to consumer electronics. IBM was using six-layer printed-circuit boards and surface-mount components in the 1960s, but Apple, for instance, didn't switch to surface-mount components until two decades later. Specifically, the Apple IIGS (1986) extensively used surface-mount components, but the Macintosh SE (1987) still used entirely through-hole components a year later.

    

    A close-up of the IOP's PROM board.

    The photo also illustrates how some integrated circuits are labeled with Specification Control Drawing (SCD) numbers (6088731-1) while others are labeled with standard part numbers (SN54LS151). This SCD number corresponds to a standard 54S10 NAND gate. The chips both have 1974 date codes (74xx), not to be confused with 7400-series part numbers.

    The photo below shows three different types of flat-pack ICs. The first type is most common, with leads extending from the top and bottom sides, similar to a modern surface-mount integrated circuit. The second package has a golden case. It is much smaller and thinner, with leads extending from all four sides. The third package also has leads from four sides, but is somewhat larger.

    

    Three types of surface-mount packages.

     ↩

14. The change in page size for the IOP is documented in Prototype IOC Functional Description, which says: "Standard 4 Pi Page Extended by Width Change from 8 to 9 inches, New Standard 120 Pin Connector".

    The photo below compares the 98-pin connector on a standard IBM 4 Pi page (top) with the 120-pin connector on the IOP page (bottom). The 120-pin has a narrower pin spacing (0.05") than the 98-pin connector (0.06"), allowing more pins in the same width. However, the 120-pin connector has more spacing between the rows of pins (0.150" vs. 0.100").

    

    The connectors on a standard IBM 4 Pi page (top) and the IOP page (bottom). The 4 Pi page is courtesy of Eric Schlaepfer. The slight waviness is just due to bent pins.

    Also note that both connectors have a peg on one side and a hollow cylinder on the other. These are used for keying, to make sure that a page cannot be plugged into the wrong slot. Each page type has a different combination; with a double connector, there are 16 possible combinations. ↩

15. The exploded view shows seven MIA (interface) pages. This doesn't make sense since there are six MIA pages for the 24 network connections, as the same document lists (in Table 4-1). That table also shows one more page in total than on the exploded view. My guess is that the system was still being changed when the document was written (some entries in the table are marked TBD), resulting in inconsistencies. ↩

16. The virtual MSC and BCE processors take turns executing on the IOP's physical processor. A 16.5 µs time interval is split into 33 slices: each BCE gets one time slice, the MSC gets 8 time slices, and one slice is used for BCE self-tests. Thus, the MSC gets much more execution time than a low-level BCE.

    

    The I/O Processor's slot timer or "wheel". Adapted from Space Shuttle Systems Handbook, 8.3.

    Each BCE and the MSC has its own register set (called local store), so the right registers are available for each slot. The physical processor is pipelined, so there are actually four slots active at any time. ↩

17. For details on the instruction sets of the MSC and BSE processors, see Prototype IOP Functional Description, chapter 2. ↩

18. The IOP used a micro-instruction that was 72 bits wide. A micro-instruction controlled the physical processor by specifying the data sources, data destinations, the ALU operations, and conditional branch actions. The table below shows the structure of the micro-instruction in detail. Note that a micro-instruction controls each component of the processor separately at a low level, so it is very different from a machine instruction. A micro-instruction also provides a degree of parallelism, since it specifies three operations for each step (ALU 1 operation, ALU 2 operation, and a conditional action).

    

    Format of a 72-bit IOP micro-instruction. From Prototype IOP Functional Description.

     ↩

19. The PROM chips are Intersil IM5624C parts. These are similar to the Signetics 82S131 and Intel 3622 parts. The front side of the page also contains nine chips labeled "D1-6605-2", probably manufactured by Harris; perhaps these are buffers. ↩

20. The Prototype Input/Output Processor Function Description lists two pages associated with microcode: "Micro Store (ROM)" (the page that I examined), and "Micro Store Page". I assume that the second page held the 512 words that didn't fit on the first page, along with the circuitry for the microcode control logic and registers. ↩

21. Why are the numbers on the PROM chips semi-ordered but also somewhat random? My hypothesis is that the original chips were numbered 1 through 36 in sequence, but when chips needed to be replaced for software patches, each new chip received the next number in sequence, up to 74. ↩

22. With flat-pack ICs, an IOP board can hold up to 20 ICs per row, so 100 ICS on a board and 200 ICs on a double-sided page. With the larger DIP packages, the PROM page holds just 45 ICs. Since DIPs are taller (thicker), the page has only a single board. This shows the large density advantage of flat-pack ICs over DIP ICs.

    The density of this page is slightly better because there are a few (15) flat-pack ICs mounted on the back of the PROM board (below). The flat-pack ICs had to be mounted between the rows of DIPs to avoid the pins of the DIP ICs. Because DIPs use through-hole mounting, their pins exit the back side of the board. The large two-pin packages above and below are decoupling capacitors, filtering the power to the ICs.

    

    Back of the PROM page.

    The back side of the board also shows that the printed-circuit board is an inch smaller than the space available; note the gap on the right. Perhaps the circuit board was designed for a standard 8-inch 4 Pi page, but then mounted on the IOP's special 9-inch page. ↩

23. The NASA Office of Logic Design web page has a photo of a Space Shuttle board that might be from the IOP, but its source is unknown (I asked). This board is puzzling because it has the same unusual 9" form factor as the IOP pages, but it also has many differences, so it probably came from a different Shuttle system.

    

    A Space Shuttle board. Note the broken connector; the plastic on these vintage Burndy connections is very often broken. From Space Shuttle Computers and Avionics.

    The board is a dual MIA interface; it is labeled "ADPTR. INTFC. DUAL MUX", part number "A538A762-02". This part number does not appear in the IOP documentation, and has a different format from IOP part numbers. The circuitry on the board is very similar to the IOP's interface board, with hybrid modules, transformers, and analog components. Physically, the board has the same dimensions, mounting hardware, and 120-pin connector as the IOP boards. However, the board doesn't have the test point connector at the top and the ICs are arranged haphazardly, instead of in uniform rows, so it doesn't look like it was manufactured by IBM. Moreover, the number of ICs is much smaller. On the other hand, it uses the same 54LS395 4-bit shift register chips (labeled 6088913). I would think that this was a prototype board for the IOP's board, except both boards are from 1976, based on the component dates.

    My current hypothesis is that this board was the MIA network interface in a different Space Shuttle component, probably the MDM (Multiplexer/Demultiplexer); the MDM contained a "Serial MIA" board built by Singer-Kearfott. Note that the board has Singer hybrid modules; since Singer-Kearfott invented the MIA network, it makes sense that their modules would be on an interface board. Another possibility is that this board was part of the Shuttle's IMU (Inertial Measurement Unit), which was built by Singer-Kearfott. The IMU communicated with the MDM via a serial I/O line that was very similar to the MIA protocol, but had some differences.

    Singer, by the way, is the same Singer that builds sewing machines. How did they end up making advanced components for the Space Shuttle? (Not to mention nuclear missile guidance systems.) In the 1960s, Singer diversified into defense and computers; in 1968, Singer acquired Kearfott, a defense company that built inertial navigation systems. The Singer-Kearfott SKC-2000 computer was considered for the Space Shuttle, but IBM's AP-101 was selected instead. Singer-Kearfott built the Inertial Measurement Units (IMUs) for the Space Shuttle. In 1987, Singer sold its Kearfott Guidance & Navigation division to the Astronautics Corporation. Kearfott still produces guidance and navigation systems, such as the inertial navigation system for the Global Hawk UAV and the Trident II submarine-launched ballistic missile. After a 1987 takeover and two bankruptcies, Singer is back to just sewing machines, now part of the SVP Worldwide sewing machine company. ↩

24. Bonus photo of Peter Kogge working on the I/O Processor:

    

     ↩