Inside a Titan missile guidance computer

I've been studying the guidance computer from a Titan II nuclear missile. This compact computer was used in the 1970s to guide a Titan II nuclear missile towards its target or send a Titan IIIC rocket into the proper orbit. The computer worked in conjunction with an Inertial Measurement Unit (IMU), a system of gyroscopes and accelerometers that tracked the rocket's position and velocity.1

The guidance computer, from Steve Jurvetson's collection. Multiple connectors on top link the computer to the IMU and the rest of the rocket. The cover panels are protected by anti-tamper stickers so I probably voided the warranty by opening it. (Click any photo for a larger image.)

This computer, called the Magic 352, is a 20"×16"×9" black box2 weighing 80 pounds, surprisingly heavy for something used in a rocket.4 Its sturdy aluminum case alone weighs 20 pounds. Internally, the computer is divided into thirds. The front section holds the processor and the core memory storage. There is no microprocessor in this computer; the processor is built from hundreds of simple integrated circuits. The back section of the computer holds the interface boards, mostly analog circuitry to connect to the rest of the rocket.5 Unexpectedly, the middle section is mostly empty space.6 The computer was made by Delco, a division of General Motors3 that built a whole line of "Magic" aerospace computers.

The digital side

The computer's front cover is held on by 18 screws. Removing them reveals the computer's processor boards and core memory. On the left are seven circuit boards with TTL digital logic. In the middle are two core memory modules, each holding 8192 words of 24 bits. Two memory electronics boards are next to the memory. At the right is the computer's switching power supply.

The front side of the computer, showing the circuit boards, core memory modules, and the power supply. The boards are identified with the code that is printed on each board.

The circuit boards have alphanumeric codes on them; PR1 through PR6 are probably processor boards 1 through 6. It's unclear what "IOC" stands for; the IOC board looks like the other digital logic boards, but also has a circuit that's probably the computer's clock. The "ME" and "CME" boards appear to have high-current driver circuitry for the core memory modules, so "ME" could be "memory electronics".

Information on the Magic 352 computer is hard to obtain7 but it uses 24-bit words (plus a parity bit), and it uses 2's complement fixed point. It has 57 instructions (probably two per word) and can do an add/subtract in 6 microseconds. The processor has six index registers.

The photo below shows one of the digital logic boards; the other digital boards are similar. Each board has integrated circuits on both sides, so the back looks about the same. (My photo album of all the boards is here.) Each side of the board has space for 5 rows of 13 chips, for up to 130 chips per board. The printed circuit board appears to have six layers; two wiring layers and a ground plane for the chips on each side. Connections between the two sides are done through the 99 connections at the top of the board rather than vias. The boards are covered with conformal coating to protect the circuitry; decades later, the coating still smells strongly of turpentine. The edges of the boards are metalized and slide tightly into card guides, providing a path for heat to escape since there is no fan. The digital boards have a 198-pin connector at the bottom that plugs into the backplane, while the interface boards (discussed later) have a smaller 128-pin connector.

Processor board PR1.

The boards are filled with TTL chips, probably MSI (medium-scale integration) chips such as counters, adders, or shift registers. Note that this computer does not contain a microprocessor chip, but has a processor built from simple building blocks. (In the 1970s, minicomputers were commonly built from boards of TTL chips.) From the part numbers on the chips, they appear to be manufactured by Signetics, in a CC2100 series. Unfortunately, even after extensive searching I couldn't find any documentation on these part numbers. (Please let me know if you have information on them.)

Some of the chips used by the computer. The PCB traces are visible in between the chips. The 7802 date code indicates they were manufactured the second week of 1978.

One interesting feature of the boards is they are keyed to ensure that a board can't be plugged into the wrong slot. The keying is implemented by splitting a hex nut in half. The circuit board and the backplane connector have matching halves, so the board can only be inserted into the right slot. There are six ways to split a hex nut corner-to-corner, and two hex nuts (one on the top and one on the bottom), making 36 possible keying combinations. The photo below shows part of the backplane with the boards removed so the connectors and half hex nuts are visible. Note that each connector has hex nuts at a different angle for the keying.

The half hex nuts fixed to the top and bottom of each connector are used to ensure each board is plugged into the right slot. Also note the cable of white and colored wires connecting the backplane to the external connectors on top of the computer. These slots are on the interface side of the computer.

Core memory8

This computer uses magnetic core memory for storage (in contrast to the earlier Titan ASC-15 computer, which used a rotating magnetic drum). Core memory was the dominant form of computer storage from the 1950s until it was replaced by semiconductor memory chips in the 1970s. Core memory was built from thousands of tiny ferrite rings called cores, with one bit stored in each core. A core was magnetized either clockwise or counterclockwise to store a value. Cores were arranged in a grid called a core plane; energizing a specific row wire and column wire selected the particular core where the two wires crossed.

The photo below shows a closeup of the tiny magnetic cores in the Titan computer. There are four wires through each core: the vertical and horizontal red wires form the grid to select a core. Two colorful horizontal wires pass through each core in the plane: the sense line (used for reading) and the inhibit line (used for writing). You can see these wires looping from row to row at the right.

Closeup of the cores in a core plane. The cores appear glossy because they are covered in conformal coating.

In a core memory, multiple planes are stacked together, one plane for each bit in a word. In most computers, the core planes were welded or soldered together into a block, but the Titan computer's core memory was built with an unusual patented technique: the cores and the circuitry were mounted on a long flexible printed circuit board that was folded accordion-style. This construction technique allows a core memory module to be opened like a book to access the cores and circuitry.

The core module unfolds like a book. The circuitry and core planes are on a flexible printed circuit board that is folded accordion-style and wrapped around metal carriers.

If you view the core memory module as a book, each "page" is constructed from a metal plate with the flexible printed circuit board wrapped over both sides. There are 6 of these "pages", so there are 12 core memory planes similar to the one below. Careful counting shows there are 128 horizontal wires and 128 vertical wires through the core plane, so there are 16,384 cores below. The 128 vertical wires are visible at the top and bottom, running loosely from plane to plane. Note that these are the delicate wires through the cores, passing continuously and unprotected through the entire set of core planes. The 128 horizontal core wires are gathered into bundles to run from plane to plane; the left bundle proceeds downward, and the right bundle proceeds upward.

One plane in the core memory has 16,384 cores. It consists of eight smaller regions ("mats"); each mat has 32×64 cores.

To the right of the cores (above) is the circuitry to handle that plane. This circuitry includes sense amplifiers to read the signals from the core plane, and inhibit drivers for writing data to the plane. These integrated circuits are mounted on the same flexible PCB as the core planes.

The flexible printed circuit board is attached to standard rigid printed circuit boards at both ends; these boards form the outside of the module. The end boards also have connectors that plug into the backplane, providing the connection between the core modules and the computer. The photo below shows one of the end boards. Note that this board has just half the cores of a normal board.9 The reason is that this board holds the parity bit, while the other 12 planes each hold two bits. Thus, the complete module holds words of 24 bits plus one parity bit, with 8192 words in the module. The computer has two core modules, so it holds a total of 16K words.10

This board at the end of the core module has half of the regular core plane. Note the numerous connections to the left of the core; the 128 horizontal wires are connected to the circuit board here. The packages at the far left each hold 8 diodes.

The interface circuitry

Turning the computer around reveals the circuit boards behind the back panel. These interface boards are wired to the connectors on top of the computer. Through these interfaces, the computer receives velocity and attitude pulses from the inertial measurement unit (IMU). The computer sends analog control signals to various actuators, as well as discrete (binary) signals to other parts of the rocket for thrusters, staging, and other functions. On the left is the power supply. The power supply receives power from the rocket through the connector on top of the computer and the cable to the power supply.

Cards in the back of the computer provide interfaces between the computer and external components. Each card has a three-letter code on it, but the meanings are unknown. The cables between the backplane and the connectors on top of the computer are behind the indicated supports.

In contrast to the digital boards, which all appear similar, the interface boards have a wide variety of circuits. The CTL, MUI, and ADL boards are covered in TTL chips, similar to the boards in the digital section. The rest of the interface boards, however, are crammed with analog components such as transistors, capacitors, resistors, diodes, and hybrid modules, along with a few TTL chips. The interface boards have the analog components on the front only (probably because there isn't enough clearance on the back) and usually a few TTL integrated circuits on the back. I traced out some of the circuitry on the "AGO" board below and found 18 current-controlled outputs connected to TTL interface chips in the middle of the board. This board probably provides binary "discrete" outputs.

The AGO interface board; the "AGO" label is at the top left. Note the different keying on the half-nuts on either side of the connector.

The VMX board below has four mysterious 6-pin black hybrid modules along with numerous large capacitors. It's unclear what function this board has, or why it needs so many capacitors.

The VMX interface board. Like the other boards, it is covered with a thick conformal coating. The connector at the bottom is much narrower than the connectors on the digital boards.

The CON board uses hybrid modules including a large red "Angstrohm" module that has hand-lettered labeling on it.

The "Angstrohm" module has 11 numbered pins, 3 "Z" pins, and a "BAE" pin.

Power supply

The computer uses a switching power supply to efficiently convert the missile's power (probably 28 volts) to the voltages required by the computer. The power supply is surprisingly heavy, about 15 pounds. Much of the weight is probably metal needed to dissipate heat since there is no fan.

The switching power supply used by the computer. The two cable connectors provide power to the digital and interface sides of the computer. The power supply receives electricity through the connector on the front.

Inside, the power supply is packed with inductors and transformers, power transistors, and circuit boards. A stack of filter capacitors in large metal cans is visible at the left in the photo below. The inductors and transformers don't look like the inductors in commercial power supplies, but are black blocks.

The switching power supply used by the computer.

Several circuit boards control the power supply. They use metal-can integrated circuits, unlike the integrated circuits in commercial power supplies. The part numbers on these integrated circuits didn't turn up anything useful so they may be custom military parts. The boards are covered with a conformal coating to protect them against humidity and other threats. The conformal coating gives a shiny golden color to the integrated circuits.

Closeup of a board in the power supply.

The power supply probably generates 5 volts for the TTL chips, along with a higher voltage to drive the core memory, and multiple voltages for the interface circuits.

History and background

In this section, I summarize the complex history of the Titan missile and rocket, and its various guidance computers. The Titan missile, deployed from 1959 to 1987 was the largest ICBM deployed by the United States and delivered a 9 megaton nuclear bomb. To get a sense of how large the Titan was, the currently-deployed Minuteman missile weighs a third as much and its warhead has 1/25 the yield.

Test launch of a Titan II from a silo. U.S. Air Force photo.

For much of its life, the Titan II's guidance computer was the IBM ASC-15 (Advance System Controller), dating to 1962. This was a 27-bit serial, transistor-based computer using discrete components in welded encapsulated modules. For storage, it used a rotating magnetic drum that held 3,840 words. This computer was used on the Titan II and Titan III, as well as the early Saturn I flights.11

The ASC-15 computer. It was emerald green in color. Photo from IBM Corporate Archives, via Saturn I Guidance and Control Systems.

Around 1964, the Titan II missile was modified for use as a satellite launcher called the Titan III. The most visible change was the addition of two solid rocket boosters for many Titan III launches. The first Titan III flights continued to use the ASC-15 guidance computer, but the project switched to the Univac 1824M Digital Flight Control System. This computer was more powerful and able to handle flight control as well as guidance and navigation. It first flew on Titan IIIC on Feb 9, 1969. However, the Univac 1824 project ended in 1969 due to cost and schedule over-runs.

Titan IIIC launch with an unmanned Gemini capsule, as part of the MOL project (1966). Photo from NASA.

Meanwhile, the AC Spark Plug division of General Motors developed the Magic family of computers for airborne guidance starting in 1962; I wrote a detailed article on the Magic computers. Delco used some of these computers in an inertial measurement unit (IMU) guidance system called the Delco Carousel.12 The Carousel IV was a popular navigation system, used on commercial planes including the 747, 707, and DC-8. The Carousel IV used the Magic 311 computer (1967) and then the Magic 351 computer (1970).

The Carousel IV navigation system (with the Magic 351 computer) was turned into a military navigation system called the Carousel V, using the Magic 352 missile guidance computer (MGC). (This is the computer I examined in this blog post.) For space use, this system became the Universal Space Guidance System (USGS). The Titan IIIC rocket switched from the Univac computer to the USGS, first flying with it on December 13, 1973 (details). After its use on the Titan III, the USGS system was retrofitted onto the Titan II missile, replacing the obsolete ASC-15 (details) in a project called RIVET HAWK (1975-1976).

To summarize, the Titan program used several different computers as techology advanced, ending up with the computer I examined in the 1970s.

Conclusion

Aerospace computers are mostly ignored in computer histories, even though they used a lot of innovative technologies. This Titan missile, for instance, computer used flexible PCBs in its core memories. It also had surface-mounted integrated circuits, years before they were common in commercial electronics. Building computers out of TTL chips became a technological dead end, however, as the capabilities of CMOS integrated circuits increased exponentially, following Moore's law.

You can see photos of the full set of boards here; the interface boards are worth examining due to their varied circuitry. I announce my latest blog posts on Twitter, so follow me @kenshirriff for future articles. I also have an RSS feed. Thanks to Steve Jurvetson. for supplying the computer.

Notes and references

1. Guidance systems use a variety of algorithms, with earlier low-power computers using simple guidance algorithms, while later computers used more complex algorithms that provided increased accuracy and flexibility. The Titan II used "delta" guidance, a simple guidance algorithm for low-power computers. In this guidance system, the algorithm attempts to keep the missile on a pre-computed path, using a third-order polynomial to steer back to the correct path.

   The Titan IIIC required complex guidance software since the flight went through multiple stages. A typical Titan IIIC mission put a satellite into a geosynchronous orbit at an altitude of 19,323 nautical miles. To do this, the rocket launched and ascended to a parking orbit between 80 and 235 nautical miles, using Stage 0 (the boosters), Stage 1, and Stage 2. The rocket then used Stage 3 to move to an elliptical transfer orbit with an apogee of 19,323 nautical miles. Another rocket burn put the vehicle into a circular orbit at this altitude. Finally, the payload separated from the rocket, putting the satellite into geosynchronous orbit. The point is that the guidance computer needed to perform many different guidance tasks, as well as controlling the various rocket stages.

   The overall Titan IIIC guidance algorithm is called "explicit" guidance, where an explicit solution is computed during flight to reach the desired end result. (I haven't been able to determine if the Titan II switched to this guidance algorithm when the computer was upgraded.)

   For an overview of guidance algorithms, see this document (p225) as well as Titan IIIC Guidance. For a more humorous explanation, see "The Missile Knows Where It Is At All Times." ↩

2. For more information on the physical characteristics of the Magic 352 computer, see Space Tug Equipment Data Bank page 58. ↩

3. It's difficult to sort out the permutations of Delco, AC Spark Plug, AC Electronics, AC Delco, and so forth. AC Spark Plug started in 1908 and became a division of General Motors in 1927. It was named after Albert Champion who also started Champion spark plugs. AC Spark Plug's Milwaukee manufacturing facility became AC Electronics in 1965, with a focus on inertial navigation (details). Meanwhile, Dayton Engineering Laboratories (Delco) was founded in 1909, and acquired by General Motors in 1918. GM's defense systems laboratory was started in 1962 and merged into Delco Systems Operations in Goleta (where this Titan guidance computer was built). In 1970, the Delco Radio Division and AC Electronics Division of General Motors Corporation were consolidated into a new Delco Electronics Division. In 1985, GM purchased Hughes Aircraft and merged it with Delco to form Hughes Electronics, which was sold to Raytheon in 1997. ↩

4. The photo below shows the label on the computer, serial number 69. The "CP-1331/DJW" designation is a military component designator. The "CP" indicates a computer unit and 1331 is the model number. The "DJW" is an "AN System" military designation for a guidance system, specifically "Missile/Drone Electromechanical Flight Control Equipment".

   

   The label from the Titan missile guidance computer.

   The computer also has a repair label showing it was last repaired on March 14, 1986.

   

   The repair label on the computer.

   Each removable panel was protected with tamper-proof seals:

   

   The sticker says "DO NOT BREAK SEAL". I broke the seals.

   The computer also had an attached service tag. The penalty for removing the tag is up to a year in prison, so it's worse than a mattress tag.

   

   Serviceable Tag—Materiel.

    ↩

5. At the back left of the computer is a fill valve, used to pressurize the computer with nitrogen to 5 PSI above ambient. The valve appears to be a Schrader valve, the same as on an automobile tire. Before opening the computer, I vented the nitrogen and found that the computer was still pressurized decades later. ↩

6. The underside of the computer has an access panel for the cables in the central section. The photo below shows the view looking up through this access panel, showing the connectors on top of the computer, as well as the cables attached to them. This part of the computer is almost entirely empty space. The backplane for the interface side of the computer is visible in the bottom of the photo; the boards plug into the other side.

   

   View into the central part of the computer showing the cabling.

   Most of the connectors on top of the computer are 61-pin circular MIL-Spec connectors. Note the keying pins sticking out of the circular shell below. Each connector has different keying to prevent attaching a cable to the wrong connector. The power input uses a 31-pin connector with larger pins that support higher current.

   

   One of the connectors on the computer, labeled "J5".

   Most of the connectors currently have yellow plastic caps, while two have metal screw caps. I think that the metal caps are for test connectors that would remain covered in flight, while the plastic caps are temporary covers for connectors that would be cabled up in flight. The test connectors are wired to the digital side of the computer. ↩

7. I couldn't find many details on the Magic 352 computer, but there is some information in Guidance and controls for an Interim Upper Stage (IUS) page 339, and Titan IIIC Guidance page 15. ↩

8. I'm a fan of core memory and have written about the core memory in the Saturn V LVDC, the Apollo Guidance Computer, the IBM 1401, and the IBM System/360, if you want to read more about core memory. ↩

9. The wiring topology of the core memory module is worth noting. Because the parity end board has half of a regular core plane, it has 64 Y wires instead of 128. These 64 wires pass through the cores and then do a U-turn, returning to the next plane as the other half of the 128 wires. The 128 X wires, on the other hand, pass through the cores and then are terminated on the board. The board at the other end terminates the 128 Y wires (as two logical groups of 64) and the other end of the 128 X wires. Both boards have numerous diode packages for these wires. ↩

10. I calculated that the computer's two core memory modules hold a total of 16K words of 24 bits plus parity. This matches the Magic 352 memory size specified in this article. However, another document says the Titan IIIC computer has 16K of memory with 2K erasable (it's unclear if these numbers are bytes or words). There's a patent related to the Titan computer describing a core memory that combines DRO (destructive read out, i.e. RAM) and NDRO (non-destructive read out, i.e. ROM). The ROM is implemented by omitting cores to store 0 bits. I believe the ROM was an optional feature, so you could get 14K of ROM and 2K of RAM, for instance. ↩

11. The Gemini space flights (1964-1966) used a Titan II GLV missile, but the guidance system was entirely different. Gemini removed the Titan II inertial guidance and replaced it with a General Electric Mod IIIG radio guidance system, for guidance from the ground (details). The Gemini capsule contained the Gemini Guidance Computer (OBC), built by IBM. ↩

12. The Carousel IMU got its name because the inertial platform rotated at 1 RPM (like a carousel) to reduce drift errors (details). Here is a photo of a commercial Delco Carousel. The Titan computer was connected to an IMU that was probably similar inside, but packaged in a black box that resembled the computer but more cubical. ↩

The Delco Magic line of aerospace computers

This post is a summary of the Magic line of computers, produced by Delco / General Motors from 1962 to the 1980s. These computers were developed for navigation, guidance, and control of rockets, missiles, and aircraft. I couldn't find a good summary of all the Magic computers, so I've collected information from various sources here. This article probably isn't of interest to most people as it's more of a footnote that grew out of control but I'm putting it here for reference.

MAGIC I

MAGIC I (1961-1963) was designed for ballistic missile guidance and was the "first complete airborne computer to have its logic functions mechanized exclusively with integrated circuits". It used 2,098 Fairchild Micrologic integrated circuits, the first commercial IC family. These integrated circuits were very simple, such as a three-input NOR gate, a flip flop, or a half adder. MAGIC I was a compact computer weighing about 35 pounds with a volume of .64 cubic feet. It used 90 watts of power. It was a serial computer, operating on one bit at a time, which made it slow but reduced the hardware requirements. It used 24-bit words, as they determined that 24 bits provided sufficient accuracy. It had 4K words of core memory storage. Instructions were 12 bits, with two instructions per word. An addition operation took 70µs.

Diagram of MAGIC I computer. From MAGIC: An advanced computer for spaceborne guidance systems.

MAGIC II

MAGIC II (1965) was a serial 24-bit computer used in the P-3A and F-8 aircraft. It weighed 35 pounds, had a volume of 0.5 cubic feet, and used 90 watts. Storage was 4K words of ROM and 256 words of magnetic core. It was constructed from about 1300 simple integrated circuits: buffers, counter adapters, double gates, half adders, and half shift. It took 38µs to add. Its simple instruction set (below) had 22 instructions. Like the MAGIC I, instructions were 12 bits, with two instructions per word.

Instruction set of the MAGIC II computer. From "Organization of MAGIC II".

Magic III

Magic III (1963-) was a family ranging from simple serial computers to high-performance parallel computers. (The Magic name appears to have lost the all-caps starting with Magic III.) These computers covered a wide variety of architectures, word sizes, and instruction sets. They ranged from slow serial computers that processed one bit at a time to parallel computers that processed a word at a time (as most computers do, not to be confused with parallel processing).

Magic 301 (1963, serial, 16-bit), It was used in the KT-70 missile guidance system in the P-3C, A-7, and F-105 aircraft, as well as the L-1011 guidance system and the SRAM nuclear short-range attack missile. It weighed 5.2 pounds, was 0.1 cubic feet, and used 39 watts. Addition took 24µs. The computer was very compact: 4.9"×3.2"×8.8". It had 1792 8-bit words, expandable to 2048 words. Instructions were 8 bits while data words were 16 bits.

Magic 311 (1967, serial, 12-bit instructions, 24-bit data with two parity bits): It had core memory holding 6144 words of 12 bits plus parity. (It could be manufactured with ROM memory by omitting cores in the core memory to represent 0 bits.) Its instruction set had 14 instructions and it took 19.5 us to perform an add. It was used in the Delco Carousel IV inertial measurement unit (IMU) used on the 707 and 747 aircraft. The computer was 0.44 cubic feet, weighed 22 pounds and used 110 watts. Its addition time was 19.5µs.

Magic 321 (serial, 15-bit instructions, 31-bit data plus parity). It had 4K blocks of core up to 32K and ran with a 3.072 MHz clock. It had 22 instructions in its instruction set and weighed 23 pounds.

Magic 331 (parallel, 31-bit plus parity) used 15-bit instruction. It had a 1 MHz clock and up to 32K memory. It had 23 instructions in its instruction set and weighed 23 pounds. 670 of these computers were built.

The Magic 341 (1971) was a 16-bit computer, built from MOS integrated circuits. It was considered for the Space Shuttle, which ended up using IBM's AP-101 computer instead. It had 2K to 64K words of magnetic core or MOS memory. It was used in the HH-60 helicopter. It had weighed 10 pounds a volume of .12 cubic feet (4"×7"×15") and took 5µs for an addition. It had 16 instructions in its instruction set.

The Magic 351 (1970) was a 19-bit computer using MSI TTL, with 24 bits as an option. It weighed 22 pounds, was 0.42 cubic feet, and used 120 watts. It was used in the C-5B cargo plane. It had 61 instructions in its instruction set.

The Magic 352 (early 1970s) had 24-bit words (plus a parity bit), with a 16 kiloword core memory. It had 57 instructions and did an add/subtract in 6 microseconds (details). It had six index registers. The Carousel IV and Magic 351 computer were turned into a military navigation system called the Carousel V, using the Magic 352 missile guidance computer (MGC) (the computer in this blog post). For space use, this system was called the Universal Space Guidance System (USGS), and the Titan IIIC rocket switched from Univac to the USGS, first flying on December 13, 1973 (details). After its use on the Titan III, the USGS system was retrofitted onto Titan II missile, replacing the ASC-15 (details), in a project was called RIVET HAWK (1975-1976).

Magic 352, from Steve Jurvetson's collection.

The Magic 362 was used in Navy ATIGS and the F-16 fire control computer (FCC). It had 32K×16 bit semiconductor memory (24K ROM, 8k RAM). The Magic 362 and later computers supported the 16-bit MIL-STD-1750A instruction set; to reduce costs and complexity, the military standardized on this instruction set from 1980 to 1996. This instruction set (described here) is fairly extensive, with many addressing modes and floating-point support.

Magic 372 (1982) performed 666 KIPS (thousand instructions per second). It was implemented from Am2901 bit slices along with SSI and MSI chips. It was used in F-16 C/D and LANTIRN.

Magic IV

The Magic IV series was introduced around 1974, switching to an all-LSI design. It used 32K×16 bit semiconductor memory and took a 28VDC power supply It was used in the KC-135 tanker.

Magic V

The Magic V series was introduced around 1982, using a VLSI design that put the computer on 12 chips on a single board. The M572 was an extension of the M372. It had a 16-bit design and 192K of RAM, using under 5 watts. It was used on the C-17A cargo airplane for the mission computer and displays.

The Delco Magic V "computer-on-a-card" used VLSI chips. Photo from Delco ad, July 1986.

Notes

Some references on the Magic family are here, here, here, here, here, and here.

It's difficult to sort out the permutations of Delco, AC Spark Plug, AC Electronics, AC Delco, and so forth. AC Spark Plug started in 1908 and became a division of General Motors in 1927. It was named after Albert Champion who also started Champion spark plugs. AC Spark Plug's Milwaukee manufacturing facility became AC Electronics in 1965, with a focus on inertial navigation (details). Meanwhile, Dayton Engineering Laboratories (Delco) was founded in 1909, and acquired by General Motors in 1918. GM's defense systems laboratory was started in 1962 and merged into Delco Systems Operations in Goleta (where this Titan guidance computer was built). In 1970, the Delco Radio Division and AC Electronics Division of General Motors Corporation were consolidated into a new Delco Electronics Division. In 1985, GM purchased Hughes Aircraft and merged it with Delco to form Hughes Electronics, which was sold to Raytheon in 1997.

Looking inside a vintage Soviet TTL logic integrated circuit

This blog post examines a 1980s chip used in a Soyuz space clock. The microscope photo below shows the tiny silicon die inside the package, with a nice, geometric layout. The silicon appears pinkish or purplish in this photo, while the metal wiring layer on top is white. Around the edge of the chip, the bond wires (black) connect pads on the chip to the chip's pins. The tiny structures on the chip are resistors and transistors.

Die photo of the Soviet 134ЛА8 (134LA8) NAND gate integrated circuit. (Click any photo for a larger image.)

The chip is used in the clock shown below. We recently obtained this digital clock that flew on a Soyuz space mission.1 The clock displays the time on the upper LED digits and provides a stopwatch on the lower LEDs. Its alarm feature activates an external circuit at a preset time. I expected that this clock would have a single clock chip inside, but the clock is surprisingly complicated, with over 100 integrated circuits on ten circuit boards. (See my previous blog post for more information about the clock.)

Space clock from Soyuz with the cover removed.

The clock's circuit boards can be opened like a book to reveal the integrated circuits and other components, thanks to the flexible wiring harnesses that connect the boards. The integrated circuits are mostly 14-pin "flat packs" in metal packages, surface-mounted on the printed circuit boards. I wanted to know more about these integrated circuits, so I opened one up,2 took photos, and reverse-engineered the chip's circuitry.

The wiring bundles are arranged so the boards can swing apart. The quartz crystal that controls the clock's timing is visible in the upper center. The clock's power supply is on the boards at the right, with multiple round inductors.

Soviet integrated circuits

The clock is built from TTL integrated circuits, a type of digital logic that was popular in the 1970s through the 1990s because it was reliable, inexpensive, and easy to use. (If you've done hobbyist digital electronics, you probably know the 7400-series of TTL chips.) A basic TTL chip contained just a few logic gates, such as 4 NAND gates or 6 inverters, while a more complex TTL chip implemented a functional unit such as a 4-bit counter. Eventually, TTL lost out to CMOS chips (the chips in modern computers), which use much less power and are much denser.

The photo below shows a chip with its metal lid removed. The tiny silicon die is visible in the middle, with bond wires connecting the die to the pins. This integrated circuit is very small; the ceramic package is 9.5mm×6.5mm, considerably smaller than a fingernail. To open up a chip like this, I normally put it in a vise and then tap the seam with a chisel. However, in this case, the chip decapped itself—while I was looking for a hammer, the top suddenly popped off due to the pressure from the vise.

The integrated circuit with its metal lid removed, showing the tiny silicon die inside.

The chip I'm examining has the Cyrillic part number 134ЛА8 (134LA8)6. It implements four open-collector NAND gates, as shown below.4 The NAND gate is a standard logic gate, outputting a 0 if both inputs are 1, and otherwise outputting a 1. An open-collector output is slightly different from a standard output. It will pull the output pin low for a 0, but for a 1 it just leaves the output floating ("high impedance").5 An external pull-up resistor is required to pull the output high for a 1. The clock uses three of these chips: one in the quartz crystal oscillator circuit, and another functioning as inverters in another part of the clock.3

Logic diagram of the Soviet 134ЛА8 (134LA8) integrated circuit, with pin numbers.

The Soviet Union lagged about 9 years behind the US in integrated circuit development.7 The lag would have been much larger, except the Soviet Union copied many Western integrated circuits. As a result, most of the Soviet TTL chips have Western equivalents.4 However, the 134ЛА8 chip that I examined is different from Western chips8 with two unusual features. First, to reduce the number of external resistors, this chip includes two pull-up resistors on the chip that can be wired up as desired. Second, the chip shares two NAND gate inputs, which frees up the two pins used by the resistors. Thus, even though the Soviet Union was copying integrated circuits, they were also creatively designing their own chips.

Integrated circuit components

Under the microscope, the transistors and resistors of the integrated circuit are visible. The silicon die appears in shades of pink, purple, and green, depending on how different regions of the chip have been "doped". By doping the silicon with impurities, the silicon takes on different semiconductor properties, making N-type and P-type silicon. On top of the silicon, the white lines are metal traces that wire together the components on the silicon layer.

The photo below shows how a resistor appears on the silicon die. A resistor is formed by doping silicon to form a high-resistance path, the reddish line below. The longer the path, the higher the resistance, so the resistors typically zig-zag back and forth to create the desired resistance. The resistor is connected to the metal layer at both ends, while another metal passes over the resistor shown below.

A resistor on the integrated circuit die.

This chip, like other TTL chips, uses bipolar NPN transistors. These transistors have N-type silicon for the emitter, P-type silicon for the base, and N-type silicon for the collector. On the IC, the transistors are constructed by doping the silicon to form layers with different properties. At the bottom of the stack, the collector forms the bulk of the transistor, doped to form N-type silicon (the large green area below). On top of the collector, a thin region of P-type silicon forms the base; this is the reddish region in the middle. Finally, a small square N-type emitter is formed on top of the base. These layers form the N-P-N structure of the transistor. Note that the metal wiring to the collector and base is off to the side, away from the main body of the transistor.

An input transistor on the integrated circuit die. The transistor is surrounded by an isolation ring (dark color) to separate it from the other transistors.

TTL circuits typically used transistors with multiple emitters, one for each input, and this can be seen above. A multiple-emitter transistor may seem strange, but it is straightforward to build one on an integrated circuit. The transistor above has two emitters wired up. Close examination shows there are four emitters, but the two lower unused emitters are shorted to the base.

The output transistors on the chip produce the external signal from the chip, so they must support much higher current than the other transistors. As a result, they are much larger than the other transistors. As before, the transistor has a large N-type collector region (green), with a base on top (pink), and then emitter on top of the base. The output transistor has long contacts between the metal layer and the silicon, rather than the small square contacts of the previous transistor. The emitter (wired in a "U" shape) is also much larger. These changes allow more current to flow through the transistor. In the photo below, the transistor on the left has no metal layer, so its silicon features are more visible.9 The transistor on the right shows the metal wiring.

Two output transistors on the integrated circuit die. The one on the left is unused, while the one on the right is wired into the circuit by the metal layer.

How a TTL NAND gate works

The schematic below shows one of the open-collector NAND gates in the chip. In this paragraph, I'll give a brief explanation of the circuit; you can skip this if you want.10 To understand the circuit, first assume that an input is 0. The current through resistor R1 and the base of transistor Q1 will flow out through the transistor's emitter and the low input. Transistor Q2 will be off, so R3 pulls Q3's base low, turning Q3 off. Thus, the output will float (i.e. open-collector 1 output). On the other hand, suppose both inputs are 1. Now the current through R1 can't pass through an input so it will flow out the collector of Q1 (i.e. backward) and into Q2's base, turning on Q2. Q2 will pull Q3's base high, turning on Q3 and pulling the output low. Thus, the circuit implements a NAND gate, outputting 0 if both inputs are high. Note that Q1 isn't acting like a normal transistor, but instead is "current-steering", directing the current from R1 in one direction or the other.

Schematic of one gate in the integrated circuit. This is an open-collector TTL NAND gate.

The diagram below shows the components for one of the NAND gates, labeled to match the schematic. (The three other NAND gates on the chip are similar.) The wiring of the gate is simple compared to most integrated circuits; you can follow the metal traces (white) and match up the wiring with the schematic. Note the winding path from the ground pad to Q3. Q1 is a two-emitter transistor while Q3 is a large output transistor. Two unused transistors are below Q2.

The die, showing the components in a gate. Components are labeled (blue) for one of the NAND gates, while pins are labeled in red. The pull-up resistors are above and below the Vcc wire.

Conclusion

This Soviet chip from 1984 is simple enough that the circuitry can be easily traced out, illustrating how a TTL NAND gate is constructed. The downside of simple chips, however, is that the Soyuz clock required over 100 chips to implement basic clock functionality. Even at the time, single chips implemented wristwatches and alarm clocks. Now, modern chips can contain billions of transistors, providing an extraordinary amount of functionality, but making the chip impossible to understand visually.

My previous blog post discussed the clock's circuitry in detail and I plan to write more about the clock, so follow me @kenshirriff (or on RSS) for details. Until then, you can watch CuriousMarc's video showing the disassembly of the space clock:

Notes and References

1. CuriousMarc obtained the clock from an auction and it was advertised as flown to space, but we don't know which mission it was flown on. The date codes on the components inside the clock are mostly from 1983, with one from 1984, so the clock was probably manufactured in 1984. The Russian name for the clock is "Бортовые Часы Космические" (Onboard Space Clock), which is abbreviated as "БЧК". ↩

2. Don't worry; I didn't destroy any of the chips in the clock. We bought duplicate chips on eBay for reverse-engineering. I was surprised that most of these 1980s-era chips are not too hard to obtain. ↩

3. I don't see any obvious reason why the 134ЛА8 chip was used instead of an inverter chip. Surprisingly, even though the 7404 hex inverter chip was extremely common in US designs, the clock doesn't use any inverter chips at all. ↩

4. For more information on Russian integrated circuits, including the ones used in the clock, see the databook Интегральные микросхемы и их зарубежные аналоги (Integrated circuits and their foreign counterparts). (The title makes it explicit that they were copying foreign chips.) Be warned that the databook's description of the 134ЛА8 has a few typos. ↩↩

5. One reason to use open-collector gates is to get an AND gate "for free". Connecting outputs together produces a wired-AND; if any output is a 0, the tied-together output is a 0. (Tying together NAND gates is equivalent to AND-OR-INVERT logic.)

   Open-collector outputs can also be used on a bus, where multiple devices or boards can write signals to a bus line (as in the Xerox Alto) without electrical conflict. This use is obsolete, though; tri-state outputs provide much better performance. ↩

6. One nice thing about Russian ICs is that the part numbers are assigned according to a rational system, unlike the essentially random numbering of American integrated circuits. Two letters in the part number indicate the function of the chip, such as a logic gate, counter, flip flop, or decoder. For example, consider the label "Δ134 ЛA8A". The series number, 134, indicates the chip is a low-power TTL chip. The "Л" (L) indicates a logic chip (Логические), with "A" indicating the NAND gate subcategory. Finally, "8" indicates a specific type of NAND chip in the ЛA category. As with American chips, the "0684" date code on the chip indicates that it was made in the 6th week of 1984. ↩

7. Two CIA reports (1974 and 1986) provide information on the lag between Soviet IC technology and Western technology. "Microcomputing in the Soviet Union and Eastern Europe", ABACUS, 1985, discusses how the Soviet Union copied American microprocessors, especially Intel ones. ↩

8. The 7400 series includes several quad open-collector NAND gate chips, such as the 7401, 7403, 7426, 7438, and 7439. These are all different from the Soviet chip. A die photo of the 74S01 is here; I think the Soviet chip has a much nicer layout. ↩

9. The integrated circuit has a few unused transistors. In addition, the input transistors have 4 emitters, but only two of them are used. This is probably so the same silicon die can be used to manufacture multiple integrated circuits by changing the metal layer. For instance, the 4-emitter transistors could be used for 3- or 4-input NAND gates. Alternatively, the unused transistors could be used to create a hex inverter chip. ↩

10. For a detailed explanation of how TTL gates work, see this page. ↩

The core memory inside a Saturn V rocket's computer

The Launch Vehicle Digital Computer (LVDC) had a key role in the Apollo Moon mission, guiding and controlling the Saturn V rocket. Like most computers of the era, it used core memory, storing data in tiny magnetic cores. In this article, I take a close look at an LVDC core memory module from Steve Jurvetson's collection. This memory module was technologically advanced for the mid-1960s, using surface-mount components, hybrid modules, and flexible connectors that made it an order of magnitude smaller and lighter than mainframe core memories.2 Even so, this memory stored just 4096 words of 26 bits.1

A core memory module from the LVDC. This module stored 4K words of 26 data bits and 2 parity bits. It weighs 2.3 kg (5.1 pounds) and measures about 14 cm×14 cm×16 cm (5½"×5½"×6"). Click on any photo for a larger version.

The race to the Moon started on May 25, 1961 when President Kennedy stated that America would land a man on the Moon before the end of the decade. This mission required the three-stage Saturn V rocket, the most powerful rocket ever built. The Saturn V was guided and controlled by the Launch Vehicle Digital Computer3 (below), from liftoff into Earth orbit, and then on a trajectory towards the Moon. (The Apollo spacecraft separated from the Saturn V rocket at that point, ending the LVDC's role.)

The LVDC mounted in a support frame. The round connectors are visible on the front side of the computer. There are 8 electrical connectors and two connectors for liquid cooling. Photo courtesy of IBM.

The LVDC was just one of several computers onboard the Apollo mission. The LVDC was connected to the Flight Control Computer, a 100-pound analog computer. The Apollo Guidance Computer (AGC) guided the spacecraft to the Moon's surface. The Command Module contained one AGC while the Lunar Module contained a second AGC7 along with the Abort Guidance System, an emergency backup computer.

Multiple computers were onboard an Apollo mission. The Launch Vehicle Digital Computer (LVDC) is the one discussed in this blog post.

Unit Logic Devices (ULD)

The LVDC was built with an interesting hybrid technology called ULD (Unit Logic Devices). Although they superficially resembled integrated circuits, ULD modules contained multiple components. They used simple silicon dies, each implementing just one transistor or two diodes. These dies, along with thick-film printed resistors, were mounted on a half-inch-square ceramic wafer to implement a circuit such as a logic gate. These modules were a variant of the SLT (Solid Logic Technology) modules developed for IBM's popular S/360 series of computers. IBM started developing SLT modules in 1961, before integrated circuits were commercially viable, and by 1966 IBM produced over 100 million SLT modules a year.

ULD modules were considerably smaller than SLT modules, as shown in the photo below, making them more suitable for a compact space computer.4 ULD modules used ceramic packages instead of SLT's metal cans, and had metal contacts on the upper surface instead of pins. Clips on the circuit board held the ULD module in place and connected with these contacts.5 The LVDC and associated hardware used more than 50 different types of ULDs.

SLT modules (left) are considerably larger than ULD modules (right). A ULD module is 7.6 mm × 8 mm.

The photo below shows the internal components of a ULD module. On the left, the circuit traces are visible on the ceramic wafer, connected to four tiny square silicon dies. While this looks like a printed circuit board, keep in mind that it is much smaller than a fingernail. On the right, the black rectangles are thick-film resistors printed onto the underside of the wafer.

Top and underside of a ULD showing the silicon dies and resistors. While SLT modules had resistors on the upper surface, ULD modules had resistors underneath, increasing the density but also the cost. From IBM Study Report Figure III-11.

The microscope photo below shows a silicon die from a ULD module that implements two diodes.6 The die is very small; for comparison, grains of sugar are displayed next to the die. The die had three external connections through copper balls soldered to the three circles. The two lower circles were doped (darker regions) to form the anodes of the two diodes, while the upper-right circle was the cathode, connected to the substrate. Note that this die is much less complex than even a basic integrated circuit.

Photo of a two-diode silicon die next to sugar crystals. This photo is a composite of top-lighting to show the die details, with back-lighting to show the sugar.

How core memory works

Core memory was the dominant form of computer storage from the 1950s until it was replaced by semiconductor memory chips in the 1970s. Core memory was built from tiny ferrite rings called cores, storing one bit in each core by magnetizing the core either clockwise or counterclockwise. A core was magnetized by sending a pulse of current through wires threaded through the core. The magnetization could be reversed by sending a pulse in the opposite direction.

To read the value of a core, a current pulse flipped the core to the 0 state. If the core was in the 1 state previously, the changing magnetic field created a voltage in a sense wire threaded through the cores. But if the core was already in the 0 state, the magnetic field wouldn't change and the sense wire wouldn't pick up a voltage. Thus, the value of the bit in the core was read by resetting the core to 0 and testing the sense wire. An important characteristic of core memory was that the process of reading a core destroyed its value, so it needed to be re-written.

Using a separate wire to flip each core would be impractical, but in the 1950s a technique called "coincident-current" was developed that used a grid of wires to select a core. This depended on a special property of cores called hysteresis: a small current has no effect on a core, but a current above a threshold would magnetize the core. This allowed a grid of X and Y lines to select one core from the grid. By energizing one X line and one Y line each with half the necessary current, only the core where both lines crossed would get enough current to flip leaving the other cores unaffected.

Closeup of an IBM 360 Model 50 core plane. The LVDC and Model 50 used the same type of cores, known as 19-32 because their inner diameter was 19 mils and their outer diameter was 32 mils (0.8 mm). While this photo shows three wires through each core, the LVDC used four wires.

The photo below shows one core plane from the LVDC's memory.8 This plane has 128 X wires running vertically and 64 Y wires running horizontally, with a core at each intersection. For reading, a single sense wire runs through all the cores parallel to the Y wires. For writing, a single inhibit wire (explained below) runs through all the cores parallel to the X wires. The sense wires cross over in the middle of the plane; this reduces induced noise because noise from one half of the plane cancels out noise from the other half.

One core plane for the LVDC's memory, holding 8192 bits. Connections to the core plane are made through the pins around the outside. From Smithsonian National Air and Space Museum.

The plane above had 8192 locations, each storing a single bit. To store a word of memory, multiple core planes were stacked together, one plane for each bit in the word. The X and Y select lines were wired to zig-zag through all the core planes, in order to select a bit of the word from each plane. Each plane had a separate sense line for reading, and a separate inhibit line for writing. The LVDC memory used a stack of 14 core planes (below), storing a 13-bit "syllable" along with a parity bit.10

The LVDC core stack consists of 14 core planes. This stack is at the US Space & Rocket Center. Photo from NCAR EOL. I retouched the photo to reduce distortion from the plastic case.

Writing to core memory required additional wires called the inhibit lines. Each plane had one inhibit line threaded through all the cores in the plane. In the write process, a current passed through the X and Y lines, flipping the selected cores (one per plane) to the 1 state, storing all 1's in the word. To write a 0 in a bit position, the plane's inhibit line was energized with half current, opposite to the X line. The currents canceled out, so the core in that plane would not flip to 1 but would remain 0. Thus, the inhibit line inhibited the core from flipping to 1. By activating the appropriate inhibit lines, any desired word could be written to the memory.

To summarize, a core memory plane had four wires through each core: X and Y drive lines, a sense line, and an inhibit line. These planes were stacked to form an array, one plane for each bit in the word. By energizing an X line and a Y line, one core in each plane was selected. The sense line was used to read the contents of the bit, while the inhibit line was used to write a 0 (by inhibiting the writing of a 1).9

The LVDC core memory module

In this section, I'll explain how the LVDC core memory module was physically constructed. At its center, the core memory module contains the stack of 14 core planes shown earlier. This is surrounded by multiple boards with the circuitry to drive the X and Y select lines and the inhibit lines, read the bits from the sense lines, detect errors, and generate necessary clock signals.11

An exploded view of the memory module showing the key components. An MIB (Multilayer Interconnection Board) is a 12-layer printed circuit board. From Saturn V Guidance Computer Progress Report Fig 2-43.

Memory Y driver panel

A word in core memory is selected by driving the appropriate X and Y lines through the core stack. I'll start by describing the Y driver circuitry and how it generates a signal through one of the 64 Y lines. Instead of having 64 separate driver circuits, the module reduces the amount of circuitry by using 8 "high" drivers and 8 "low" drivers. These are wired up in a "matrix" configuration so each combination of a high driver and a low driver selects a different line. Thus, the 8 high drivers and 8 low drivers select one of the 64 (8×8) Y lines. The footnote12 has more information on the matrix technique.

The Y driver board (front) drives the Y select lines in the core stack.

The closeup view below shows some of the ULD modules (white) and transistor pairs (golden) that drive the Y select lines. The "EI" module is the heart of the driver; it supplies a constant voltage pulse (E) or sinks a constant current pulse (I) through a select line.14 A select line is driven by activating an EI module in voltage mode at one end of the line and an EI module in current mode at the other end. The result is a pulse with the correct voltage and current to flip the core. It takes a hefty pulse to flip a core; the voltage pulse is fixed at 17 volts, while the current is adjusted from 180 mA to 260 mA depending on the temperature.13

Closeup of the Y driver board showing six ULD modules and six transistor pairs. Each ULD module is labeled with an IBM part number, the module type (e.g. "EI"), and an unknown code.

The board also has error-detector (ED) modules that detect if more than one Y select line is driven at the same time. Implementing this with digital logic would require a complicated set of gates to detect if two or more of the 8 inputs are high. Instead, the ED module uses a simple semi-analog design: it sums the input voltages using a resistor network. If the resulting voltage is above a threshold, the output is triggered.

A diode matrix is underneath the driver board, containing 256 diodes and 64 resistors. This matrix converts the 8 high and 8 low pairs of signals from the driver board into connections to the 64 Y lines that pass through the core stack. Flex cables on the top and bottom of the board connect the board to the diode matrix. Two flex cables on the left (not visible in the photo) and two flex cables on the right (one visible) connect the diode matrix to the core stack.15 The flex cable visible on the left connects the Y board to the rest of the computer via the I/O board (described later) while a small flex cable on the lower right connects to the clock board.

Memory X driver panel

The circuitry to drive the X lines is similar to the Y circuitry, except there are 128 X lines compared to 64 Y lines. Because there are twice as many X lines, the module has a second X driver board underneath the one visible below. Although the X and Y boards have the same components, the wiring is different.

This board and the similar one underneath drive the X select lines in the core stack.

The closeup below shows that the board has suffered some component damage. One of the transistors has been dislodged, a ULD module has been broken in half, and the other ULD module is cracked. The wiring is visible inside the broken module as well as one of the tiny silicon dies (on the right). This photo also shows vertical and horizontal circuit board traces on several of the board's 12 layers.

A closeup of the X driver board showing some damaged circuitry.

Underneath the X driver boards is the X diode matrix, containing 288 diodes and 128 resistors. The X diode matrix uses a different topology than the Y diode board to avoid doubling the number of components.16 Like the Y diode board, this board contains components mounted vertically between two printed circuit boards. This technique is called "cordwood" and allows the components to be packed together closely.

Closeup of X diode matrix showing diodes mounted vertically using cordwood construction between two printed circuit boards. The two X driver boards are above the diode board, separated from it by foam. Note how the circuit boards are packed very closely together.

Memory sense amplifiers

The photo below shows the sense amplifier board on top of the module.17 It has 7 channels to read 7 bits from the memory stack; an identical board below processes another 7 bits, for 14 bits in total. The job of the sense amplifier is to detect the small signal (20 millivolts) generated by a flipping core, and turn it into a 1-bit output. Each channel consists of a differential amplifier and buffer, followed by a differential transformer and an output latch. At the left, the 28-conductor flex cable connects to the memory stack, feeding the two ends of each sense wire into the amplifier circuitry, starting with an MSA-1 (Memory Sense Amplifier) module. The discrete components are resistors (brown cylinders), capacitors (red), transformers (black), and transistors (golden). The data bits exit the sense amplifier boards through the flex cable on the right.

The sense amplifier board on top of the memory module. This board amplifies the signals from the sense wires to produce the output bits.

Memory inhibit drivers

The inhibit board is on the underside of the core module and holds the inhibit drivers that are used for writing to memory. There are 14 inhibit lines, one for each plane in the core stack. To write a 0 bit, the corresponding inhibit driver is activated and the current through the inhibit line prevents the core from flipping to a 1. Each line is driven by an ID-1 and ID-2 (Inhibit Driver) module and a pair of transistors. The high-precision 20.8Ω resistors at the top and bottom of the board regulate the inhibit current. The 14-wire flex cable on the right connects the drivers to the 14 inhibit wires in the core stack.

The inhibit board on the bottom of the memory module. This board generates the 14 inhibit signals used during writing.

Memory clock driver

The clock driver is a pair of boards that generate the timing signals for the memory module. Once the computer starts a memory operation, the various timing signals used by the memory module are generated asynchronously by the module's clock driver. The clock driver boards are on the bottom of the module, between the core stack and the inhibit board so it is hard to see the boards.

The clock driver boards are below the core memory stack but above the inhibit board.

The photo above looks between the clock driver boards; the inhibit board is on the bottom. The blue components are multi-turn potentiometers, presumably to adjust timings or voltages. Resistors and capacitors are also visible on the boards. The schematic shows several MCD (Memory Clock Driver) modules, but I can't see any modules on the boards. I don't know if that is due to the limited visibility, a change in the circuitry, or another board with these modules.

Memory input-output panel

The final board of the memory module is the input-output panel (below), which distributes signals between the boards of the memory module and the remainder of the LVDC computer. At the bottom, the green 98-pin connector plugs into the LVDC's memory chassis, providing signals and power from the computer. (Much of the connector's plastic is broken, exposing the pins.) The distribution board is linked to this connector by two 49-pin flex cables at the bottom (only the front cable is visible). Other flex cables distribute signals to the X-driver board (left), the Y-driver board (right), the sense amplifier board (top), and inhibit board (underneath). The 20 capacitors on the board filter the power supplied to the memory module.

The input-output board is the interface between the memory module and the rest of the computer. The green connector at the bottom plugs into the computer, and these signals are routed through flat cables to other parts of the memory module. This board also has filter capacitors.

Conclusion

The LVDC's core memory module provided compact, reliable storage for the computer. The lower half of the computer (below) was filled by up to 8 core memory modules. This allowed the computer to hold a total of 32 kilowords of 26-bit words, or 16 kilowords in redundant high-reliability "duplex" mode.18

The LVDC held up to eight core memory modules. Photo at US Space & Rocket Center, courtesy of Mark Wells.

The core memory module provides an interesting view of a time when 8K of storage required a 5-pound module. While this core memory was technologically advanced for its time, the hybrid ULD modules were rapidly obsoleted by integrated circuits. Core memory as a whole died out in the 1970s with the advent of semiconductor DRAMs.

The contents of core memory are retained when the power is disconnected, so it's likely that the module still holds the software from when the computer was last used, even decades later. It would be interesting to try to recover this data, but the damaged circuitry poses a problem so the contents will probably remain locked inside the memory module for decades more.

I announce my latest blog posts on Twitter, so follow me @kenshirriff for future articles. I also have an RSS feed. For an explanation of core memory, see CuriousMarc's video where we wire up a core plane and demonstrate how it works. I've written before about core memory in the IBM 1401, core memory in the Apollo Guidance Computer, and core memory in the IBM S/360. Thanks to Steve Jurvetson for supplying the core array.

Notes and references

1. A word size of 26 bits may seem bizarre, but in the 1960s computers hadn't yet standardized on bytes and word sizes that were a power of two. Business computers often used 6-bit characters, while aerospace computers typically used whatever word size provided the necessary accuracy. ↩

2. It's interesting to compare the size of the LVDC's core memory to IBM's commercial core memories, which I wrote about here. The 128-kilobyte expansion for the IBM S/360 Model 40 computer required an additional cabinet weighing 610 pounds and measuring 62.5"×26"×60". An LVDC core memory module holds 4K words of 26 bits, equivalent to 13 kilobytes. Doing the math, the LVDC has 1/12 the weight and 1/40 the volume per byte. The core stack itself was very similar between the LVDC and the S/360 machines; the difference in weight and volume comes from the surrounding electronics and packaging. ↩

3. For more information on the LVDC, see the Virtual AGC project's LVDC page. Also see the interesting SmarterEveryDay video on the LVDC. Fran Blanche did an extensive investigation into an LVDC circuit board. ↩

4. The SLT modules in my photograph are mounted on an SMS card, rather than the expected SLT card. SMS cards were IBM's previous generation of circuit cards and normally used discrete germanium transistors. However, even after the introduction of SLT in 1964, IBM needed to support older computers with SMS cards. To reduce costs, they started building old-style SMS cards that used the more modern SLT modules. The point is that SLT modules were usually packed densely on multiple-layer circuit boards, rather than the low-density SMS card in the photo. ↩

5. One question is why did IBM use SLT modules instead of integrated circuits? The main reason was that integrated circuits were still in their infancy, having been invented in 1959. In 1963, SLT modules had cost and performance advantages over integrated circuits. However, SLT modules were viewed outside IBM as backward compared to integrated circuits. One advantage of SLT modules over integrated circuits was that the resistors in SLT were much more accurate than those in integrated circuits. During manufacturing, the thick-film resistors in SLT modules were carefully sand-blasted to remove resistive film until they had the desired resistance. SLT modules were also cheaper than comparable integrated circuits in the 1960s. By 1969, IBM started using integrated circuits, which they called MST (Monolithic Systems Technology). IBM packaged their integrated circuits in SLT-style metal packages, rather than the industry-standard DIP epoxy packages. Chapter 2 of IBM's 360 and Early 370 Systems discusses the history of SLT modules in great detail. ↩

6. Curiously, the ULD modules in the core memory did not contain any sealant inside. In contrast, the ULD modules examined by Fran Blanche were filled with pink silicone inside. ↩

7. It's interesting to compare the AGC to the LVDC since they took two very different approaches to computer design and manufacture. Both computers had rectangular metal boxes, magnesium-lithium for the LVDC and magnesium for the AGC. Physically, the LVDC was about twice the size (2.2 cubic feet vs 1.1 cubic feet) even though they were both about 70 pounds. The LVDC used 138 Watts and was liquid-cooled, while the AGC used 55 watts and was cooled by conduction. The LVDC used 26-bit words compared to 15 bits in the AGC. One big architectural difference was that the LVDC was a serial computer, operating on one bit at a time, while the AGC operated on all bits in parallel (like most computers). Another important difference was that the LVDC used triple redundancy for reliability, while the AGC had no hardware fault handling. Both computers used a 2.048 MHz clock, but the LVDC was considerably slower because it was serial: 82 µs for an add operation compared to 23.4 µs for the AGC. The LVDC had up to 8 core memory modules, holding 4K words each. The AGC's core memory was only 2K words. However, the AGC also had 36K words of read-only storage in its hardwired core rope modules. (The LVDC did not use core rope.)

   The two computers were constructed in very different ways. The AGC was built from integrated circuits, while the LVDC used hybrid ULD modules. The AGC's logic gates were RTL (resistor-transistor logic) NOR gates, while the LVDC's were slightly more advanced DTL (diode-transistor logic) AND-OR-INVERT gates. While the AGC used two types of ICs (a dual NOR gate and a sense amplifier), the LVDC used many different types of modules.

   The AGC's circuit boards were encapsulated into rectangular modules, while the LVDC's circuit boards plugged into a backplane in a more standard way. The AGC's backplane was wire-wrapped by machine, while the LVDC's backplane was a 14-layer printed circuit board.

   IBM engaged in political battles, attempting to replace MIT's AGC with the LVDC. IBM argued that the AGC wasn't reliable enough compared to the triple-redundant LVDC. According to MIT, however, the AGC could run a guidance program 10 to 20 times faster than the LVDC, use half the memory, and provide more accuracy (by using double precision). MIT argued that the LVDC wasn't powerful enough to replace the AGC. In the end, the AGC survived the "naysayers" and was used on the Apollo spacecraft, while the LVDC had its role in the Saturn V rocket. The "showdown" is described in more detail here.  ↩

8. The Smithsonian website states that the core plane is approximately 4"×7"×1", but that can't be right since the entire memory module is less than 7" wide. The Study Report page 3-43 says each plane is 5.5"×3.5×0.15", which seems accurate. ↩

9. The book Memories That Shaped an Industry discusses the history of core memory at IBM. ↩

10. The LVDC has 26-bit words, each word consisting of two 13-bit syllables. Its core memory is described as holding 4K words, where each word is 26 data bits and 2 parity bits. However, the core memory is physically constructed to store 8K syllables (13 data bits and 1 parity bit). Thus, two memory accesses are required to read a complete word. An instruction is one 13-bit syllable so an instruction can be read in a single memory cycle. Thus, executing a typical instruction requires three memory accesses: one for the instruction and two for the data. (Keep in mind that reading from core memory erases the data, so a memory access consists of a read followed by a write to restore the data.) ↩

11. Much of the memory-related circuitry is in the LVDC's computer logic, not the memory module itself. In particular, the computer's logic contains registers to hold the address and data word and convert between serial and parallel. It also contains circuitry to decode the address into drive lines, as well as to generate and check parity. ↩

12. Core memories typically used a "matrix" approach to reduce the number of circuits required to drive the X and Y select lines. The diagram below demonstrates this technique for the vertical lines in a hypothetical 9×5 core array. There are three "high" drivers (A, B and C), and three "low" drivers (1, 2 and 3). If driver B is energized positive and driver 1 is energized negative, current flows through the core line highlighted in red. By selecting a different pair of drivers, a different line is energized. In a large array, this approach significantly reduces the number of line drivers required.

    

    The "matrix" approach reduces the number of line drivers required.

    When using a matrix approach, each line must have diodes to prevent "sneak paths" through the cores. To see the need for diodes, note that in the example above current could flow from B to 2, up to A and finally down to 1, for instance, incorrectly energizing multiple lines and flipping the wrong cores. By putting diodes on each line, reverse current paths such as 2 to A can be blocked. Also note that writing core memory requires current pulses in the opposite direction from reading. Supporting this requires additional diodes in the opposite direction. ↩

13. Because the characteristics of ferrite cores change with temperature, the memory module adjusts the current based on temperature, from 260 mA at 10 °C to 180 mA at 70 °C. A sensor in the stack detects the temperature, causing a TCV regulator (Temperature Controlled Voltage) to generate a voltage ranging from 6 V at 10 °C to 4 V at 70 °C. The TCV control voltage is fed into each EI module, causing the current to drop 1.33 mA per °C.  ↩

14. It's unclear why the driver boards use EI modules as well as ID-2 (Inhibit Driver) modules, since a separate board implements the inhibit drivers. The earlier schematics show just the EI modules. (See Laboratory Maintenance Instructions for LVDC Vol. II (1965) page 10-164 for the schematics.) The inhibit driver is similar to the current sink in the EI driver, so I suspect the ID-2 module is being used to boost the current.  ↩

15. For reference, this footnote provides details of the Y driver signal routing. There are 8 high drive signals and 8 low drive signals generating the 64 Y select lines through the core stack. However, the current through the select line needs to go both ways, so cores can be flipped both directions. Thus, the drive signals are in pairs, one from the "E" side (voltage source) of the EI chip and one from the "I" side (current sink). These 32 signals go from the driver board to the diode matrix through two 16-wire flat cables. The diode board is connected to 64 Y select lines, but each line has two ends. These 128 connections are through four 32-wire flat cables, two on the left and two on the right. The two cables connected to the front side of the diode matrix wrap around to the far side of the stack, while the two cables connected to the back side of the diode matrix go to the near side of the stack. Thus, alternating select lines go through the stack in opposite directions. ↩

16. The X and Y diode matrices use a different wiring topology. There are 64 Y lines through the core stack. They are matrixed with 8 drivers at one end and 8 at the other end. The Y board has a diode pair (electrically) at each end of the 64 Y lines, so it has 256 diodes and 128 wires to the Y lines. (Because a line needs to be driven in either direction, one diode is required in each direction, making a pair at each end.)

    On the other hand, there are 128 X lines through the core stack, matrixed with 16 drivers at one end and 8 at the other end. To avoid doubling the number of diodes used, the X board only has a diode pair at one end of each of the 128 X lines. At the other end, groups of 8 X lines are tied together directly, forming 16 groups with one diode pair is used for each group. Thus, there are 256 diodes in the matrix, as well as 32 diodes associated with the 16 groups. As far as wires between the diode matrix and the core stack, there are 128 wires for the diode-connected end, and 32 wires corresponding to the grouped end. See Figures 10-42 and 10-43 in the Laboratory Maintenance Instructions for LVDC Vol. II (1965) for schematics.

    The X driver board is connected to other boards and the core stack through multiple flex cables. The cable on the right links the driver board to the rest of the computer via the I/O board. The top edge of the board has a 24-wire flex cable to the diode matrix, with a second 24-wire cable at the bottom. At the bottom, another smaller flex cable receives signals from the timing board underneath the core stack. The flex cables between the diode matrices and the core stack are not visible: there is a 16-wire cable and a 64-wire cable to the stack at the top and similar cables at the bottom.

    There is an important difference between the X and Y wiring. The four flat cables between the X diode matrix and the core planes went vertically, from the top and bottom of the matrix. The flat cables from the Y diode matrix went horizontally, from the sides of the matrix. In this way, the X and Y cables were attached to orthogonal sides of the core planes, connecting to the orthogonal X and Y wires. ↩

17. A special handle was produced to insert, remove, or carry the memory module. Because the memory modules were delicate and mounted with little clearance, this tool was developed to manipulate the module safely. This handle slides over the four shoulder screws on top of the module and latches into place.

    

    The special carrying handle for the memory module. From Laboratory Maintenance Instructions for LVDC Vol. II page 4-5.

     ↩

18. One interesting feature of the LVDC was that memory modules could be mirrored for reliability. In "duplex" mode, each word was stored in two memory modules. If one module had an error, the correct word could be retrieved from the other module. While this provided reliability, it cut the memory capacity in half. Alternatively, memory modules could be used in "simplex" mode, with each word stored once.

    Note that the LVDC's circuitry was triply-redundant to detect and correct errors. However, memory only needed to be doubly redundant because parity indicated which value was incorrect. The LVDC used odd parity. Odd parity had the advantage that parity would catch a word that was stuck all 0's or all 1's. One interesting feature of the simplex and duplex memory modes is that the software could switch between them while running, even setting separate modes for instructions and data. This allowed some words to be stored in simplex mode while more important words were stored in duplex mode. However, it appears that in actual use, the entire memory would be duplexed rather than specific parts. ↩