Inside the die of Intel's 8087 coprocessor chip, root of modern floating point

Looking inside the Intel 8087, an early floating point chip, I noticed an interesting feature on the die: the substrate bias generation circuit. In this article I explain how this circuit is implemented, using analog and digital circuitry to create a negative voltage.

Intel introduced the 8087 chip in 1980 to improve floating-point performance on 8086/8088 computers such as the original IBM PC. Since early microprocessors were designed to operate on integers, arithmetic on floating point numbers was slow, and transcendental operations such as trig or logarithms were even worse. But the 8087 co-processor greatly improved floating point speed, up to 100 times faster. The 8087's architecture became part of later Intel processors, and the 8087's instructions are still a part of today's x86 desktop computers.1

I opened up an 8087 chip and took die photos with a microscope yielding the composite photo below. The die of the 8087 is fairly complex, with 40,000 transistors (according to Intel) or 45,000 transistors (according to Wikipedia). The photo shows the metal layer of the chip, the connections on top of the chip. The thickest white lines provide power and ground connections to all parts of the chip. Hidden underneath the metal are the polysilicon and silicon that form the chip's transistors. (Click the photo for a large image.)

Die photo of the Intel 8087 floating point coprocessor chip.

The bottom half of the chip holds the 80 bit wide arithmetic circuitry: an adder, shifters, mathematical constant storage and registers. The large rectangle in the middle of the chip is the microcode that controls the chip. At the top is control logic and bus circuitry that interfaced with the 8086 processor. (I'll discuss the inner workings of the 8087 in more detail in later blog posts.)

The black lines around the outside of the die photo are the tiny bond wires connecting the pads on the die to the 40 pins of the chip. By studying the 8087 datasheet, it's not too hard to figure out which pad on the die corresponds to each pin of the chip; the chip's 40 pins (numbered counterclockwise) are wired in order to 40 pads on the chip. The diagram below zooms in on the center right part of the die, labeling some of the pads. (Note that the ground and +5V power (Vcc) pads have multiple wires in parallel to carry more current.) However, one puzzle appeared—an extra pad and wire located between pads 40 and 1, not associated with any of the chip's pins.

Each pad on the die of the 8087 FPU chip is wired to one of the 40 pins of the chip. But there is one extra wire between pins 1 and 40. It is connected to the chips's substrate.

Looking at the bond wires on the chip (below) revealed that the mystery pad wasn't connected to one of the pins but to a tiny cubical block to the right of the die. Since the cube is on the same metallic base as the die, it connects to the die's underlying silicon, the substrate. I did some reverse-engineering and determined that this is part of the 8087's substrate bias circuit, which uses this connection to put a negative voltage on the substrate. The rest of this blog post explains how this circuit works.

The die of the 8087 FPU chip, showing the bond wires from the die to the package.

What is substrate bias?

High-density integrated circuits in the 1970s were usually built from NMOS transistors. The diagram below shows the structure of an NMOS transistor. The integrated circuit starts with a silicon substrate, and transistors are built on this. Regions of the silicon are doped with impurities to create diffusion regions with desired properties. The transistor can be viewed as a switch, allowing current to flow between two diffusion regions called the source and drain. The transistor is controlled by the gate, made of a special type of silicon called polysilicon. A high signal voltage on the gate lets current flow between the source and drain, while a low signal voltage blocks current flow. An insulating oxide layer separates the gate from the silicon underneath; this insulating layer will be important later. These tiny transistors can be combined to form logic gates, the components of microprocessors and other digital chips.

Structure of a MOSFET as implemented in an integrated circuit.

For high-performance integrated circuits, it was beneficial to apply a negative "bias" voltage to the substrate. 2 To obtain this substrate bias voltage, many chips in the 1970s had an external pin that was connected to -5V.3 However, engineers didn't like chips that required an inconvenient extra voltage. Even worse, chips of that era often required a third voltage,4 so systems required three power supplies to support these chips. In addition, the number of pins on ICs was limited (typically just 18 pins for memory chips), so using up two pins for extra voltages was unfortunate. Part of the solution, developed around the end of the 1970s, was for chips to generate the negative bias voltage internally. The result was chips that used a single convenient +5V supply, making engineers happier.

Inside the 8087's substrate bias circuit

You might wonder how a chip can turn a positive voltage into a negative voltage. The answer is a circuit called the charge pump, which uses capacitors to generate the desired voltage.

The 8087's bias generator has two charge pumps working in alternation. The schematics below show the operation of one of the charge pumps. The charge pump is driven by an oscillating signal (Q) and its inverse (Q). In the first step, the upper transistor is switched on, causing the capacitor to charge to 5 volts with respect to ground. The second step is where the magic happens. The lower transistor turns on, connecting the high side of the capacitor to ground. Since the capacitor is still charged to 5 volts, the low side of the capacitor must now be at -5 volts, producing the desired negative voltage at the output. When the oscillator flips again, the upper transistor is turned on and the cycle repeats.5 The charge pump gets its name because it pumps charge from the output to ground. If you view the diodes as check valves, the charge pump is analogous to a manual water pump.

Schematic of the charge pump used in the Intel 8087 to provide negative substrate bias.

To reverse engineer the charge pump circuitry, I examined the die with a microscope. The metal layer obscures the transistors underneath, making it difficult to see the circuitry. But by dissolving the metal layer with hydrochloric acid, I exposed the polysilicon and silicon layers, revealing the transistors and capacitors, as seen below. (The colorful regions are simply interference patterns due to some oxide that wasn't fully removed.) The die photo below shows the two charge pumps: one to the left of the pad, and one below. Each charge pump matches the schematic above, with two diodes, a large capacitor, and two drive transistors.

The substrate bias circuit of the 8087. The metal layer has been removed in this die photo.

The capacitors are the most visible feature of the substrate bias circuitry. Although microscopic, they are huge by chip standards. The area used by the capacitors is about the same as 72 bits of register storage, over 400 transistors. Each capacitor consists of polysilicon over a silicon region, separated by insulating oxide; the polysilicon and silicon form the plates of the capacitor. In the photo, the capacitors are studded with squares; these squares are contacts between the polysilicon or silicon and the metal layer on top. (The metal layer is not visible as it was removed.)

The four drive transistors are much larger than regular transistors since they must handle high current. The red lines are the polysilicon wires forming the gates. The green lines are contacts to the metal layer, connecting the transistors to +5V or ground. The diodes next to the pad are formed from transistors by connecting the gate and drain together (details).

The charge pumps are driven by the ring oscillator at the bottom of the above image. This ring oscillator consists of five inverters in a loop as shown below. Because the number of inverters is odd, the system is unstable and will oscillate. For instance, if the input to the first inverter is 0, the output from the fifth inverter will be 1. This will flip the first inverter, and the "flip" will travel through the loop causing oscillation. To slow down the oscillation rate, two resistor-capacitor networks are inserted into the ring. Since the capacitors will take some time to charge and discharge, the oscillations will be slowed, giving the charge pump time to operate.

The ring oscillator circuit in the 8087's charge pump.

Before explaining the ring oscillator, I'll show how a standard NMOS inverter is implemented in silicon. The diagram below shows an inverter, its schematic, and how it appears on the die. The inverter uses a transistor and a pull-up resistor (which is really a transistor). If the input is low, the transistor is off and the pull-up resistor pulls the output to +5V. If the input is high, the transistor is on, pulling the output to ground. Thus, the circuit inverts the input.

How an inverter is implemented with NMOS logic, and how it appears on the chip die.

In the die photo above, the inverter's physical layout matches the schematic. The large beige regions are doped silicon. The thinner yellow areas bordered with purple are polysilicon. The input is a polysilicon wire. Where it crosses the doped silicon it forms the gate of a transistor between ground (below the input) and the output (above the input). The pull-up resistor is implemented with a transistor that has the gate and drain tied together; the indicated contact forms this connection between the transistor's polysilicon gate and its silicon drain. The polysilicon also forms the output wire. Thus, an inverter is implemented on the chip with two transistors.

The ring oscillator in the 8087 FPU chip, as seen on the die.

The photo above shows how the ring oscillator appears on the die. The five inverters are outlined. Each inverter has a different orientation to optimize the layout, but careful examination shows the same transistor and pull-up structure explained above. The resistors and capacitors for the R-C delays are also indicated. The resistors are simply transistors with a long distance between source and drain, reducing the current flow. These capacitors are constructed like the charge pump capacitors, but are much smaller; the silicon on the bottom and the polysilicon on top form the capacitor plates, separated by the thin insulating oxide layer.

Conclusions

The substrate bias generator on the 8087 chip is an interesting combination of digital circuitry (a ring oscillator formed from inverters) and an analog charge pump. Substrate bias generator circuits were introduced in the late 1970s, helping memory chips and microprocessors to operate from a single +5V supply, much more convenient than requiring three different voltages. The substrate bias generator produces a negative voltage from the positive supply voltage by using a charge pump.

While the bias generator may seem like an obscure part of 1970s computer history, bias generation is still part of modern integrated circuits but has become much more complex, with multiple carefully regulated biases in multiple power domains. There is even a standard (IEEE 1801 power format) that allows IC design tools to generate the necessary circuitry.6

Likewise, even though Intel's 8087 floating point unit chip was introduced 38 years ago, it still has a large impact today. It spawned the IEEE 754 floating point standard used for most modern floating point arithmetic, and the 8087's instructions remain a part of the x86 processors used in most computers.

I'll end with one more 8087 die photo; this one shows the polysilicon and silicon after stripping off the metal. You may recognize the substrate bias generator circuit at the center right. (Click for a large image.)

Die photo of the Intel 8087 floating point unit. The metal layer has been stripped off with acid, revealing the polysilicon and silicon underneath.

I announce my latest blog posts on Twitter, so follow me at @kenshirriff for future 8087 articles. I also have an RSS feed. Thanks to Ed Spittles and Eric Smith for comments.

Notes and references

1. The 8087 introduced a bunch of new instructions to the 8086, such as FADD (floating add), FDIV (floating divide) and FPTAN (tangent). These instructions were implemented using the 8086's ESC "escape" instruction, which was designed to let the 8086 processor interact with a coprocessor.

   The 8087 led to the IEEE 754 floating point standard in 1985; this defines the floating point used by most computers today. For more information on how the 8087 works, see The Intel 8087 numeric data processor by John Palmer or The 8087 Primer. ↩

2. Putting a negative bias voltage on the substrate had several benefits. It decreased parasitic capacitance making the chip faster, made the transistor threshold voltage more predictable, and reduced leakage current. ↩

3. Early DRAM memory chips and microprocessor chips often required three supplies: +5V (Vcc), +12V (Vdd) and -5V (Vbb) bias voltage. In the late 1970s, improvements in chip technology allowed a single supply to be used instead. For example, Mostek's MK4116 (a 16 kilobit DRAM from 1977) required three voltages while the improved MK4516 (1981) operated on a single +5V supply, simplifying hardware designs. (Amusingly, some of these chips still kept the Vbb and Vcc pins for backwards compatibility but left them unconnected.) Intel's memory chips followed a similar path, with the 2116 DRAM (16K, 1977) using three voltages and the improved 2118 (1979) using a single voltage. Similarly, the famous Intel 8080 microprocessor (1974) used enhancement-mode transistors and required three voltages. An improved version, the 8085 (1976), used depletion-mode transistors and was powered by a single +5V supply. The Motorola 6800 microprocessor (1974) used a different approach for a single supply; although the 6800 was built from the older enhancement-load transistors it avoided the +12 supply by implementing an on-chip voltage doubler, a charge pump that increased the voltage. ↩

4. The third (+12V) supply in old chips is unrelated to the substrate bias. This supply was used because early MOS integrated circuits used enhancement-mode transistors as pull-up loads in gates. These transistors couldn't pull signals all the way up to the +5V level, so chips added an an even higher +12V supply. In the mid 1970's, new technology (ion implantation) allowed the creation of depletion-load transistors, which functioned much better as pull-up loads and eliminated the need for the +12V supply. For details, see Wikipedia, StackExchange and VLSI design techniques for analog and digital circuits page 539. ↩

5. I've simplified the charge pump discussion slightly. Due to voltage drops in the transistors, the substrate voltage will probably be around -3V, not -5V. (If a chip requires a larger voltage drop, charge pump stages can be cascaded.) For the pump direction, I'm referring to current flow. If you think of it as pumping electrons, the negative electrons are being pumped the opposite direction, into the substrate. ↩

6. Bias generators are now available as IP blocks that can be licensed and be plugged into a chip design. For more information on bias in modern chips, see Body bias, Multi bias domain implementation, or this presentation. ↩